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Thu, 13 Aug 2026 09:57:28 -0700 (PDT) X-Received: by 2002:a17:90b:1b0c:b0:38e:542:6485 with SMTP id 98e67ed59e1d1-3931e2069c3mr6772329a91.12.1786640247833; Thu, 13 Aug 2026 09:57:27 -0700 (PDT) Received: from [192.168.1.6] ([122.171.19.66]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3931cd468cesm4121774a91.7.2026.08.13.09.57.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 13 Aug 2026 09:57:27 -0700 (PDT) Message-ID: <7e42defa-f712-4d90-a328-344d9cee66fa@oss.qualcomm.com> Date: Thu, 13 Aug 2026 22:27:18 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 15/15] ARM: dts: qcom: Add initial device tree for Kuno SoC To: Dmitry Baryshkov , Krzysztof Kozlowski Cc: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Michael Turquette , Stephen Boyd , Brian Masney , Taniya Das , Georgi Djakov , Bartosz Golaszewski , Linus Walleij , Thomas Gleixner , Radu Rendec , Robert Marko , Guru Das Srinagesh , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org References: <20260809-kuno-soc-support-v1-0-5e0ede4a0c72@oss.qualcomm.com> <20260809-kuno-soc-support-v1-15-5e0ede4a0c72@oss.qualcomm.com> <20260813-generous-romantic-asp-be92e8@quoll> <3zqx6nxp4wmzej3nokfggoji7nihosru6yyaquvwjfvtylf2fq@ucr235faztbl> Content-Language: en-US From: Hardeep Sharma In-Reply-To: <3zqx6nxp4wmzej3nokfggoji7nihosru6yyaquvwjfvtylf2fq@ucr235faztbl> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=Ovh/DS/t c=1 sm=1 tr=0 ts=6a7df779 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=o18eRHaKI7CUylSTromjKw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=TlKW4IKFNLZu7OIdjWUA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODEzMDEyMiBTYWx0ZWRfX7h06/h/A7Bif DO527BtZ5eZkvPqBoTm4ZlW8vY3XR7p6dEKoJWMm4m7sh74vBBcymO+xCSKLlU2qshw7jRofkGM GDKqiA9QgDWQkrslSbgLgeoF/M2yeqw= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODEzMDEyMiBTYWx0ZWRfXwKCDlPcYz3HQ UiwMzPzdtf12WPMTcO8MgtHk/R+txVxW9eT8eXdgi/jnFPm5KLcWtRHCP6Sl64zakgTMFWkiioP X9F3Jfo7kSmP5vu0EUslf8xMECcRrrlw/ZDbLCGN7adWiUHudotFhvr5hNnMAIcTMvfi03d1tgb hcVw+ziyk+sz6gb5Pb47Of56GJ8FmZwjb3xxXKpmGEEkfRO8zFvnnvGM3+S2PYqHoxwoTPvODFH qdWqKztVDDRBAMQ0rsdtl/JJO7e5okSe9x+Qhhu30tH3qWxsOzWpSXFjVZQPOSp2t4i9OaDPF79 duP/D/n7VE/0fy2nngSqkMha1/nIWF7UphETdOP0bWraBFOxHB35O0SWg3+zDao8wMddlasC/f9 q3wGfoJD2omoo4jXZHSzHZdlEq/LB1cZoYWmV0z/9+baj0rgFNq19NqoHE9sHzSx+uwy4Twhak3 tmWhY+PAD6XcMXtqfhA== X-Proofpoint-ORIG-GUID: qfeu0zkCibChx72MXruvEhGknsn7bGA7 X-Proofpoint-GUID: qfeu0zkCibChx72MXruvEhGknsn7bGA7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-13_05,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608130122 On 8/13/2026 9:31 PM, Dmitry Baryshkov wrote: > On Thu, Aug 13, 2026 at 11:44:28AM +0200, Krzysztof Kozlowski wrote: >> On Tue, Aug 11, 2026 at 04:13:40AM +0300, Dmitry Baryshkov wrote: >>> On Sun, Aug 09, 2026 at 12:57:14PM +0530, Hardeep Sharma wrote: >>>> Add SoC-level DTSI (qcom-kuno.dtsi) and IDP board DTS >>>> (qcom-kuno-idp.dts) for the Qualcomm Kuno SoC. >>>> >>>> Peripherals included in this initial set: >>>> - Single Cortex-A7 CPU with PSCI idle states >>>> - RPMh RSC with clock controller, power domains, and BCM voter >>>> - GCC (Global Clock Controller) >>>> - TLMM pin controller (110 GPIOs) >>>> - Interconnect (aggre-noc, cnoc-main) >>>> - GENI UART console (QUP SE3) >>>> - SMEM, hardware spinlocks (TCSR mutex) >>> This is pretty limited without any storage. Does it NAND? >> It has serial connection. this is enough for a start. At least one >> communication interface is needed for early upstreaming. > Yes, but then, as I wrote, it is pretty useless without the backing > storage. Also, it would be nice if we new the future plan. Is it going > to stop at this point? Is it going to be expanded in the next few weeks? > Will we see a spread of conflicting patches 'arm64: qcom: kuno: add > support for foo' with foo in 'USB, PCI, remoteproc, NAND, etc.'. Hi Dmitry Thanks for review. Kuno is 32-bit ARM (Cortex-A7), so follow-ups will be `ARM: qcom: kuno:`, not `arm64:`. This series is the minimum-viable base (console + core infra), following the sdx55/sdx75 pattern. Storage and the other drivers will follow in coordinated series on top of this base. Best wishes, Hardeep Sharma