From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 944C637B402 for ; Thu, 22 Jan 2026 10:23:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769077391; cv=none; b=u+inywPpLh1Kz9ULs5AfgAX4njHMLl9/ms37cbPskgQTcgetw/XS+ML7/Zn+QXwTCR+Jvdyr6h7HrL0k2B0EEY4xNB3DJ4OdN+ct741Yq4Ov6CSJuGAnxJ2Xk8BiWIY27KRr0shQjuY43J2Ejpsd7ruX7qKuSRwgrzwYuPQ99Go= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769077391; c=relaxed/simple; bh=6qtRhx1BPm2hyI1kQ6FyHOW1MWuEMlO2nUQjxqPZacs=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=UCqx4p6U1dbqs6/8QnsdRkvKa84Czk1k7vdW9CTVKfwt99/mcBhyN7WW5W8VPwuYYxQRUG/FGRZzgkUJfnYDBvtfSFRO2rcS49Kmf5xk7HBGm5D95lz34DgBTqsGzpUWRj/mYu14fqWa0I1fS6jas4xC3y6r9JUT7sx+FtJVI4Q= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.arm.com; spf=pass smtp.mailfrom=foss.arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A99B5339; Thu, 22 Jan 2026 02:22:56 -0800 (PST) Received: from [10.1.194.63] (e142334-100.cambridge.arm.com [10.1.194.63]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 580EE3F740; Thu, 22 Jan 2026 02:23:02 -0800 (PST) Message-ID: <7e47cccb-5d9f-470d-9de1-8caddc300646@foss.arm.com> Date: Thu, 22 Jan 2026 10:23:01 +0000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/2] arm64: mte: Set TCMA1 whenever MTE is present in the kernel To: Carl Worth , Catalin Marinas , Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Taehyun Noh , usama.anjum@foss.arm.com, Peter Collingbourne References: <20251030-mte-tighten-tco-v2-0-e259dda9d5b3@os.amperecomputing.com> <20251030-mte-tighten-tco-v2-2-e259dda9d5b3@os.amperecomputing.com> Content-Language: en-US From: Usama Anjum In-Reply-To: <20251030-mte-tighten-tco-v2-2-e259dda9d5b3@os.amperecomputing.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 15/01/2026 11:07 pm, Carl Worth wrote: > Set the TCMA1 bit so that access to TTBR1 addresses with 0xf in their > tag bits will be treated as tag unchecked. > > This is important to avoid unwanted tag checking on some > systems. Specifically, SCTLR_EL1.TCF can be set to indicate that no > tag check faults are desired. But the architecture doesn't guarantee > that in this case the system won't still perform tag checks. > > Use TCMA1 to ensure that undesired tag checks are not performed. This > bit was already set in the KASAN case. Adding it to the non-KASAN case > prevents tag checking since all TTBR1 address will have a value of 0xf > in their tag bits. > > This patch has been measured on an Ampere system to improve the following: > > * Eliminate over 98% of kernel-side tag checks during "perf bench > futex hash", as measured with "perf stat". > > * Eliminate all MTE overhead (was previously a 25% performance > penalty) from the Phoronix pts/memcached benchmark (1:10 Set:Get > ration with 96 cores). > > Reported-by: Taehyun Noh > Suggested-by: Catalin Marinas > Signed-off-by: Carl Worth Fixes tag is required here so that the fix traverses to the stable kernels. I've not found the most appropriate commit: 973b9e373306 ("arm64: mte: move register initialization to C") bfc62c598527 ("arm64: kasan: allow enabling in-kernel MTE") In my opinion, bfc62c598527 should be in the fixes-by tag. At a minimum, the back porting should be done till 973b9e373306. > --- > arch/arm64/mm/proc.S | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S > index 5d907ce3b6d3..22866b49be37 100644 > --- a/arch/arm64/mm/proc.S > +++ b/arch/arm64/mm/proc.S > @@ -48,14 +48,14 @@ > #define TCR_KASAN_SW_FLAGS 0 > #endif > > -#ifdef CONFIG_KASAN_HW_TAGS > -#define TCR_MTE_FLAGS TCR_EL1_TCMA1 | TCR_EL1_TBI1 | TCR_EL1_TBID1 > -#elif defined(CONFIG_ARM64_MTE) > +#ifdef CONFIG_ARM64_MTE > /* > * The mte_zero_clear_page_tags() implementation uses DC GZVA, which relies on > - * TBI being enabled at EL1. > + * TBI being enabled at EL1. TCMA1 is needed to treat accesses with the > + * match-all tag (0xF) as Tag Unchecked, irrespective of the SCTLR_EL1.TCF > + * setting. > */ > -#define TCR_MTE_FLAGS TCR_EL1_TBI1 | TCR_EL1_TBID1 > +#define TCR_MTE_FLAGS TCR_EL1_TCMA1 | TCR_EL1_TBI1 | TCR_EL1_TBID1 > #else > #define TCR_MTE_FLAGS 0 > #endif >