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Sun, 10 May 2026 14:23:15 -0700 From: Nicolin Chen To: , , , CC: , , , , , , , , , , Subject: [PATCH v5 5/6] iommu/arm-smmu-v3: Retain CR0_SMMUEN during kdump device reset Date: Sun, 10 May 2026 14:23:04 -0700 Message-ID: <7e617d6227e5fc3ca431dcb2febe9f0692c5d6ae.1778416609.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0002256E:EE_|SA3PR12MB8811:EE_ X-MS-Office365-Filtering-Correlation-Id: 0beb1941-c54d-45ae-b6d1-08deaeda5e4b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|82310400026|36860700016|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: BD+uMR+mco5YfVRKn0qx+H8M7pHo2KSKwGzk7ZhnTRny67/DtbElWtpMpou5PCBFrdrtFHShVzeuXn5c6imRBT5gKdogB+INIFhaXlKrasbYbkV73WQSPvXl0hVkGC/6y+Vz/JhuPzUTYwC+le3noCpHNzTLg3inJpYXsu7q6eMqX7pAVg1No5cMEKVP+AGfw/qi7KejLzu5ejXaz9oiNVevF+QVxy/YAHhcuV8E8okcBQ1t3arM9Es/+lLJuN++BWcTsTz27JrD9cVSCHZADC370J7bH7qqkbbXdpmW32e3BlZtTDDnfKxJ8CvnqPynIF0EiW67hORdG9zCUYM74Ku5RhPFEkrjaF6BP731cM2YoFV4/iA+JaGdK4oMKM1IB11xcVRa3us0iToRNoi0YpgPl5Ke9H8Zc7mhCcdKQZq26nrnVwPdQIw/IxKlEspOzHk6SZG2lK3KkKS23rHj+Na5n2n01NydlACWQ+mSjgsxGAEeXh5tgBdMFA5t/1Fl6NQrqleW66iEO9tiNNEzzBJyzhwLiA/nNqcHzJlIlt/I4WYfmQscAOgcHp1S2uHdeE1ODK2LM2Ak113R+PxorB6fh3hZ3ZFFQ0HzwZcC0xhdIbze3X8210/q6NdkYCaXpcNdvnmqmhF89i2TfKMTcXmCl14TEDMyG3jUiurpa9b+mEFhYaXYCxqH030p8e8835H9P+9vN266ZIWzVxUAtxOlocAVh5dlUF0tXuLcGVc= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(1800799024)(82310400026)(36860700016)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: DnnHXeASZWiZQQTI2rnfzRyMKtrZWCmWT1soGmteuka6roegP7qBFoHjgzw6M4rmkjN8QBA2GWM6Ge5mZOJUP4zuHuFXDQIJWk2Ne4vWIhWeyIKhtWpAALl/MMUiX/PbdUmqfXmHjo4I6vADgqC9FgKEQATAevWbc/zOpePU3hML/slqlQSHPnw6YqDCdp/u7/rvfo/+igrvO96H1r1RaBlWxLyltoE3RDi49o7HS5Q9HS9Q2RCcKdKrsTBpdvqRLcjLmmEyofDlnFlQRV0xudzXU4/dw9IozfEyrUAgTm9Q4fLoGocfkLHmzVYFL7YecUYsHONzBrG9MlpG+LTDUa+MfdZBYPGzgaG57yjZsEOJoyeVapr20ZD0P0iZ1so0kfJA3OJLp2htoRyu+UAA/4CS/VBDjXX+7qSN5cLO6Ycf3nkY/c1PehzD7r3KS4cH X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2026 21:23:23.9485 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0beb1941-c54d-45ae-b6d1-08deaeda5e4b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0002256E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB8811 When ARM_SMMU_OPT_KDUMP_ADOPT is detected, do not disable SMMUEN and skip the CR1/CR2/STRTAB_BASE update sequence in arm_smmu_device_reset(). Those register writes are all CONSTRAINED UNPREDICTABLE while CR0_SMMUEN==1, so leaving them intact lets in-flight DMAs continue to be translated by the adopted stream table. Initialize 'enables' to 0 so it can carry CR0_SMMUEN in kdump case. Then, preserve that when enabling the command queue. Clear latched gerror bits if necessary. Fixes: b63b3439b856 ("iommu/arm-smmu-v3: Abort all transactions if SMMU is enabled in kdump kernel") Cc: stable@vger.kernel.org # v6.12+ Signed-off-by: Nicolin Chen Reviewed-by: Kevin Tian --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 47 +++++++++++++++++++-- 1 file changed, 44 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index b7298218bac9a..bb8cc580e7ad8 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -5151,11 +5151,28 @@ static void arm_smmu_write_strtab(struct arm_smmu_device *smmu) static int arm_smmu_device_reset(struct arm_smmu_device *smmu) { int ret; - u32 reg, enables; + u32 reg, enables = 0; struct arm_smmu_cmdq_ent cmd; - /* Clear CR0 and sync (disables SMMU and queue processing) */ reg = readl_relaxed(smmu->base + ARM_SMMU_CR0); + + /* + * In a kdump case (set when CR0_SMMUEN=1 and !GERROR_SFM_ERR), retain + * CR0_SMMUEN to avoid aborting in-flight DMA, and CR0_ATSCHK to carry + * on the ATS-check policy. + * + * According to spec, updating STRTAB_BASE/CR1/CR2 when CR0_SMMUEN=1 is + * CONSTRAINED UNPREDICTABLE. So, skip those register updates and rely + * on the adopted stream table from the crashed kernel. + */ + if (smmu->options & ARM_SMMU_OPT_KDUMP_ADOPT) { + dev_info(smmu->dev, + "kdump: retaining SMMUEN for in-flight DMA\n"); + enables = reg & (CR0_SMMUEN | CR0_ATSCHK); + goto reset_queues; + } + + /* Clear CR0 and sync (disables SMMU and queue processing) */ if (reg & CR0_SMMUEN) { dev_warn(smmu->dev, "SMMU currently enabled! Resetting...\n"); arm_smmu_update_gbpa(smmu, GBPA_ABORT, 0); @@ -5185,12 +5202,36 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu) /* Stream table */ arm_smmu_write_strtab(smmu); +reset_queues: + if (smmu->options & ARM_SMMU_OPT_KDUMP_ADOPT) { + /* Disable queues since arm_smmu_device_disable() was skipped */ + ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, + ARM_SMMU_CR0ACK); + if (ret) { + dev_err(smmu->dev, "failed to disable queues\n"); + return ret; + } + } + + /* + * GERROR bits are latched. Read after queue disabling so that unhandled + * errors would be visible. Ack everything prior to re-enabling the CMDQ + * as a stale CMDQ_ERR would halt the CMDQ and new command will timeout. + */ + if (is_kdump_kernel()) { + u32 gerror = readl_relaxed(smmu->base + ARM_SMMU_GERROR); + u32 gerrorn = readl_relaxed(smmu->base + ARM_SMMU_GERRORN); + + if ((gerror ^ gerrorn) & GERROR_ERR_MASK) + writel(gerror, smmu->base + ARM_SMMU_GERRORN); + } + /* Command queue */ writeq_relaxed(smmu->cmdq.q.q_base, smmu->base + ARM_SMMU_CMDQ_BASE); writel_relaxed(smmu->cmdq.q.llq.prod, smmu->base + ARM_SMMU_CMDQ_PROD); writel_relaxed(smmu->cmdq.q.llq.cons, smmu->base + ARM_SMMU_CMDQ_CONS); - enables = CR0_CMDQEN; + enables |= CR0_CMDQEN; ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, ARM_SMMU_CR0ACK); if (ret) { -- 2.43.0