Re: [PATCH v2 4/4] usb: dwc3: Notify XHCI core of tunneled status

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 7/23/26 1:01 AM, Thinh Nguyen wrote:
> On Wed, Jul 15, 2026, Konrad Dybcio wrote:
>> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>
>> The Thunderbolt framework relies on the USB core to create device links
>> for tunneled ports, so that the USB3 controller is only kept
>> runtime-resumed for the duration of the tunneling. This depends on
>> first knowing whether a connection is tunneled or native.
>>
>> Add the logic to handle that for DWC3 controllers.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>> ---
>>  drivers/usb/dwc3/core.c | 16 ++++++++++++++++
>>  drivers/usb/dwc3/core.h | 18 ++++++++++++++++++
>>  drivers/usb/dwc3/host.c | 12 ++++++++++++
>>  3 files changed, 46 insertions(+)
>>
>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
>> index fd5c2cd36c59..6ee6fce4c927 100644
>> --- a/drivers/usb/dwc3/core.c
>> +++ b/drivers/usb/dwc3/core.c
>> @@ -162,6 +162,22 @@ void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode, bool ignore_susphy)
>>  }
>>  EXPORT_SYMBOL_GPL(dwc3_set_prtcap);
>>  
>> +enum usb_link_tunnel_mode dwc3_link_tunnel_mode(struct dwc3 *dwc, u8 port)
>> +{
>> +	/* Prior versions had no CIO support */
>> +	if (!DWC3_VER_IS_WITHIN(DWC31, 191A, ANY))
>> +		return USB_LINK_NATIVE;
> 
> Refer on the feedback from the other patches, this should return
> USB_LINK_UNKNOWN instead.

My thinking here was that if there is physically no possibility of
the controller carrying a tunneled connection, it must logically be
native

>> +
>> +	/* Not all DWC3 instances have CIO HW, trust the platform firmware */
>> +	if (!device_property_present(dwc->dev, "usb4-host-interface"))
>> +		return USB_LINK_NATIVE;
> 
> Same here.

Here I can agree it's possible that the link may be either native or
tunneled, but it'd require the DT to be wrong (lacking the property)
on the XHCI side, while describing the USB4 router.

But on a second thought, the router may be internal to the SoC, but
present on a discoverable bus (e.g. PCIe), where it would appear so
long as the PCIe controller is enabled, not necessarily requiring its
own DT node. So I suppose UNKNOWN here really makes sense.

Konrad