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Wed, 07 Oct 2026 07:45:50 -0700 (PDT) X-Received: by 2002:a17:90b:4f44:b0:3a9:9f13:e960 with SMTP id 98e67ed59e1d1-3a99f13ebafmr45527a91.60.1791384350133; Wed, 07 Oct 2026 07:45:50 -0700 (PDT) Received: from [10.217.216.105] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3a8987b09e2sm5347940a91.2.2026.10.07.07.45.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 07 Oct 2026 07:45:47 -0700 (PDT) Message-ID: <7e8ea792-2336-4252-beed-7345815b0b90@oss.qualcomm.com> Date: Wed, 7 Oct 2026 20:15:39 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 5/5] phy: qcom-qmp-ufs: Add Glymur support To: Dmitry Baryshkov Cc: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Avri Altman , Bart Van Assche , Bjorn Andersson , Konrad Dybcio , gopikrishna.garmidi@oss.qualcomm.com, jagadeesh.kona@oss.qualcomm.com, Abel Vesa , Abel Vesa , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, nitin.rawat@oss.qualcomm.com, sibi.sankar@oss.qualcomm.com, Taniya Das , Konrad Dybcio References: <20261007-glymur_ufs_qcb_enablement-v3-0-84cf4f861415@oss.qualcomm.com> <20261007-glymur_ufs_qcb_enablement-v3-5-84cf4f861415@oss.qualcomm.com> Content-Language: en-US From: Pradeep Pragallapati In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA3MDA1OCBTYWx0ZWRfX1YknpUuAHyt2 ZL3Lsp+oZjytywKaKyTzIJ968NqS2tDoRwes8OC/+/D3P6mB/ZcsiibOjZcz04ojiEcYsp+0Wxg 9hAgXrpre5JlAq/qAbs8kyJyJLHU9dxS/121QqHeqgdfvQua64cX3cGH2nDNw1WbO5QnFjl1fVF VKFhWJ0jhY4ytHX2wBcyjgIb7mimfFFaAyF6ZubI4hcU40tU0IvnOAYaizLDM7i7rAZeZkl6iIm qtIOEwi75KAnVWhkJQzsh3Yl87vVaR2N/c+6aiEgVxYPsNGY7VBkKmtNQ3sZaXqPFM6tPPm2hRM bfybm4/4ojdiz6GEVYoXxrzaYJxDX4osFYTAAFh7Z3cb1KkoRY5ftEZTUvMuENoP4ag2UN6ciw1 Sl2yWixPZcWFA0jMSka6P+kR+EG7WQ3yT9fUkIbu/2s1GNnJxUQiiao/gClr4HwD0gaTxY2p+QP bl+yB4ZvTosndzS3VIQ== X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA3MDA1OCBTYWx0ZWRfX+9vLv5TktWH8 eXqdAKKwGDvb41hLuzcueq5kB66uvnR7s/+3pXXSPHSOUKIM0OFsHQYv6w4o/CIVW0AX8t4IuYo WW+bfPfJZ+Tfwqf05TTDnCYQF9JnhKs= X-Proofpoint-ORIG-GUID: JA58nMwbbgCeho3YiiD-XrUDOr1IfzjD X-Proofpoint-GUID: JA58nMwbbgCeho3YiiD-XrUDOr1IfzjD X-Authority-Analysis: v=2.4 cv=OYkNnRTY c=1 sm=1 tr=0 ts=6ac65b1f cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=JfrnYn6hAAAA:8 a=EUspDBNiAAAA:8 a=arnyFyO8AZpeLAH_8-UA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 a=1CNFftbPRP8L7MoqJWF3:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-07_04,2026-10-06_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 spamscore=0 phishscore=0 bulkscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2610070058 On 10/7/2026 7:13 PM, Dmitry Baryshkov wrote: > On Wed, Oct 07, 2026 at 05:03:02PM +0530, Pradeep Pragallapati wrote: >> >> >> On 10/7/2026 1:18 PM, Dmitry Baryshkov wrote: >>> On Wed, Oct 07, 2026 at 11:59:38AM +0530, Pradeep P V K wrote: >>>> Add the init sequence tables and config for the UFS QMP phy found in >>>> the Glymur SoC. >>>> >>>> Reviewed-by: Abel Vesa >>>> Acked-by: Konrad Dybcio >>>> Signed-off-by: Pradeep P V K >>>> --- >>>> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 99 +++++++++++++++++++++++++++++++++ >>>> 1 file changed, 99 insertions(+) >>>> >>>> + .offsets = &qmp_ufs_offsets_v6, >>> >>> So, is it a PHY using v6 offsets, but v7 registers inside? >>> >> The QSERDES RX0 register offsets on Glymur SoC are aligned with the v7 register layout offsets. >> Therefore, the v7 QSERDES RX0 register offsets are used for Glymur (similar to SM8750). > > Mention in the commit message, please. sure, i will mention it.> >> >>>> + .max_supported_gear = UFS_HS_G5, >>>> + >>>> + .vreg_list = glymur_ufsphy_vreg_l, >>>> + .num_vregs = ARRAY_SIZE(glymur_ufsphy_vreg_l), >>>> + .regs = ufsphy_v6_regs_layout, >>> >>> v7 > > This still holds. > Do you mean changing ufsphy_v6_regs_layout to ufsphy_v7_regs_layout? If so, no. ufsphy_v6_regs_layout contains the PCS register offsets, and the PCS register offsets on Glymur are aligned with ufsphy_v6_regs_layout, similar to SM8750. >>> >>>> +}; >>>> + >>>> static const struct qmp_phy_cfg milos_ufsphy_cfg = { >>>> .lanes = 2, >>>> >>> >> >> >> -- >> linux-phy mailing list >> linux-phy@lists.infradead.org >> https://lists.infradead.org/mailman/listinfo/linux-phy >