[RFC PATCH 5/6] ARM: dts: rockchip: Add RKVENC encoder to RV1126

[Daniel Golle <daniel@makrotopia.org>]

Add the encoder with its IOMMU, the VEPU power domain and the three
QoS nodes of the encoder ports. The encoder AXI clock is set to
297 MHz and the core clock to 396 MHz.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
 arch/arm/boot/dts/rockchip/rv1126.dtsi | 54 ++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/arch/arm/boot/dts/rockchip/rv1126.dtsi b/arch/arm/boot/dts/rockchip/rv1126.dtsi
index 74f238e13533c..63705291dd3ce 100644
--- a/arch/arm/boot/dts/rockchip/rv1126.dtsi
+++ b/arch/arm/boot/dts/rockchip/rv1126.dtsi
@@ -139,6 +139,21 @@ qos_sdio: qos@fe86c000 {
 		reg = <0xfe86c000 0x20>;
 	};
 
+	qos_venc_rd_m0: qos@fe870000 {
+		compatible = "rockchip,rv1126-qos", "syscon";
+		reg = <0xfe870000 0x20>;
+	};
+
+	qos_venc_rd_m1: qos@fe870080 {
+		compatible = "rockchip,rv1126-qos", "syscon";
+		reg = <0xfe870080 0x20>;
+	};
+
+	qos_venc_wr: qos@fe870100 {
+		compatible = "rockchip,rv1126-qos", "syscon";
+		reg = <0xfe870100 0x20>;
+	};
+
 	qos_iep: qos@fe8a0000 {
 		compatible = "rockchip,rv1126-qos", "syscon";
 		reg = <0xfe8a0000 0x20>;
@@ -223,6 +238,17 @@ power-domain@RV1126_PD_VO {
 					 <&qos_iep>;
 				#power-domain-cells = <0>;
 			};
+
+			power-domain@RV1126_PD_VEPU {
+				reg = <RV1126_PD_VEPU>;
+				clocks = <&cru ACLK_VENC>,
+					 <&cru HCLK_VENC>,
+					 <&cru CLK_VENC_CORE>;
+				pm_qos = <&qos_venc_rd_m0>,
+					 <&qos_venc_rd_m1>,
+					 <&qos_venc_wr>;
+				#power-domain-cells = <0>;
+			};
 		};
 	};
 
@@ -630,6 +656,34 @@ vop_mmu: iommu@ffb00f00 {
 		status = "disabled";
 	};
 
+	venc: video-codec@ffbb0000 {
+		compatible = "rockchip,rv1126-rkvenc";
+		reg = <0xffbb0000 0xf00>;
+		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru ACLK_VENC>, <&cru HCLK_VENC>,
+			 <&cru CLK_VENC_CORE>;
+		clock-names = "axi", "ahb", "core";
+		assigned-clocks = <&cru ACLK_VENC>, <&cru CLK_VENC_CORE>;
+		assigned-clock-rates = <297000000>, <396000000>;
+		resets = <&cru SRST_VENC_A>, <&cru SRST_VENC_H>,
+			 <&cru SRST_VENC_CORE>;
+		reset-names = "axi", "ahb", "core";
+		iommus = <&venc_mmu>;
+		power-domains = <&power RV1126_PD_VEPU>;
+	};
+
+	venc_mmu: iommu@ffbb0f00 {
+		compatible = "rockchip,iommu";
+		reg = <0xffbb0f00 0x40>, <0xffbb0f40 0x40>;
+		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru ACLK_VENC>, <&cru HCLK_VENC>;
+		clock-names = "aclk", "iface";
+		#iommu-cells = <0>;
+		power-domains = <&power RV1126_PD_VEPU>;
+		rockchip,disable-mmu-reset;
+	};
+
 	gmac: ethernet@ffc40000 {
 		compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a";
 		reg = <0xffc40000 0x4000>;
-- 
2.56.0