From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751320AbdKHIqf (ORCPT ); Wed, 8 Nov 2017 03:46:35 -0500 Received: from mx1.redhat.com ([209.132.183.28]:47918 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750888AbdKHIqd (ORCPT ); Wed, 8 Nov 2017 03:46:33 -0500 DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 6F0463683C Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=eric.auger@redhat.com Subject: Re: [PATCH v5 22/26] KVM: arm/arm64: GICv4: Enable virtual cpuif if VLPIs can be delivered To: Marc Zyngier , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20171027142855.21584-1-marc.zyngier@arm.com> <20171027142855.21584-23-marc.zyngier@arm.com> Cc: Mark Rutland , Christoffer Dall , Andre Przywara , Shameerali Kolothum Thodi , Christoffer Dall , Shanker Donthineni From: Auger Eric Message-ID: <7eb443d1-b247-943b-36e6-a478b7a9d78f@redhat.com> Date: Wed, 8 Nov 2017 09:46:29 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 MIME-Version: 1.0 In-Reply-To: <20171027142855.21584-23-marc.zyngier@arm.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.30]); Wed, 08 Nov 2017 08:46:33 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 27/10/2017 16:28, Marc Zyngier wrote: > In order for VLPIs to be delivered to the guest, we must make > sure that the virtual cpuif is always enabled, irrespective of the > presence of virtual interrupt in the LRs. > > Acked-by: Christoffer Dall > Signed-off-by: Marc Zyngier Reviewed-by: Eric Auger Thanks Eric > --- > virt/kvm/arm/hyp/vgic-v3-sr.c | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/virt/kvm/arm/hyp/vgic-v3-sr.c b/virt/kvm/arm/hyp/vgic-v3-sr.c > index 91728faa13fd..f5c3d6d7019e 100644 > --- a/virt/kvm/arm/hyp/vgic-v3-sr.c > +++ b/virt/kvm/arm/hyp/vgic-v3-sr.c > @@ -258,7 +258,8 @@ void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu) > cpu_if->vgic_ap1r[0] = __vgic_v3_read_ap1rn(0); > } > } else { > - if (static_branch_unlikely(&vgic_v3_cpuif_trap)) > + if (static_branch_unlikely(&vgic_v3_cpuif_trap) || > + cpu_if->its_vpe.its_vm) > write_gicreg(0, ICH_HCR_EL2); > > cpu_if->vgic_elrsr = 0xffff; > @@ -337,9 +338,11 @@ void __hyp_text __vgic_v3_restore_state(struct kvm_vcpu *vcpu) > /* > * If we need to trap system registers, we must write > * ICH_HCR_EL2 anyway, even if no interrupts are being > - * injected, > + * injected. Same thing if GICv4 is used, as VLPI > + * delivery is gated by ICH_HCR_EL2.En. > */ > - if (static_branch_unlikely(&vgic_v3_cpuif_trap)) > + if (static_branch_unlikely(&vgic_v3_cpuif_trap) || > + cpu_if->its_vpe.its_vm) > write_gicreg(cpu_if->vgic_hcr, ICH_HCR_EL2); > } > >