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Tue, 24 Jun 2025 04:42:34 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ThreadId: T4b9790859b38a261 Date: Tue, 24 Jun 2025 09:42:14 +0100 From: "Jiaxun Yang" To: "Thomas Bogendoerfer" Cc: "Maciej W. Rozycki" , "linux-mips@vger.kernel.org" , linux-kernel@vger.kernel.org, stable@kernel.org Message-Id: <7ebe1a12-5975-4ed1-8580-905662059a27@app.fastmail.com> In-Reply-To: <20250607-tlb-fix-v2-1-6751eccd86f1@flygoat.com> References: <20250607-tlb-fix-v2-1-6751eccd86f1@flygoat.com> Subject: Re: [PATCH v2] MIPS: mm: tlb-r4k: Uniquify TLB entries on init Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable =E5=9C=A82025=E5=B9=B46=E6=9C=887=E6=97=A5=E5=91=A8=E5=85=AD =E4=B8=8B=E5= =8D=881:43=EF=BC=8CJiaxun Yang=E5=86=99=E9=81=93=EF=BC=9A > Hardware or bootloader will initialize TLB entries to any value, which > may collide with kernel's UNIQUE_ENTRYHI value. On MIPS microAptiv/M51= 50 > family of cores this will trigger machine check exception and cause bo= ot > failure. On M5150 simulation this could happen 7 times out of 1000 boo= ts. > > Replace local_flush_tlb_all() with r4k_tlb_uniquify() which probes each > TLB ENTRIHI unique value for collisions before it's written, and in ca= se > of collision try a different ASID. A gentle ping :-) > > Cc: stable@kernel.org > Signed-off-by: Jiaxun Yang > --- > Changes in v2: > - Cycle ASID instead of ENTRYHI index in case of collison. > - Avoid int over flow UB (Maciej) > - Link to v1:=20 > https://lore.kernel.org/r/20250605-tlb-fix-v1-1-4af496f17b2f@flygoat.c= om > --- > arch/mips/mm/tlb-r4k.c | 56=20 > +++++++++++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 55 insertions(+), 1 deletion(-) > > diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c > index=20 > 76f3b9c0a9f0ce60c42e4a9ea8025e1283678bd1..347126dc010dd59904820d9d9e34= cdeeb011832f=20 > 100644 > --- a/arch/mips/mm/tlb-r4k.c > +++ b/arch/mips/mm/tlb-r4k.c > @@ -508,6 +508,60 @@ static int __init set_ntlb(char *str) >=20 > __setup("ntlb=3D", set_ntlb); >=20 > +/* Initialise all TLB entries with unique values */ > +static void r4k_tlb_uniquify(void) > +{ > + int entry =3D num_wired_entries(); > + > + htw_stop(); > + write_c0_entrylo0(0); > + write_c0_entrylo1(0); > + > + while (entry < current_cpu_data.tlbsize) { > + unsigned long asid_mask =3D cpu_asid_mask(¤t_cpu_data); > + unsigned long asid =3D 0; > + int idx; > + > + /* Skip wired MMID to make ginvt_mmid work */ > + if (cpu_has_mmid) > + asid =3D MMID_KERNEL_WIRED + 1; > + > + /* Check for match before using UNIQUE_ENTRYHI */ > + do { > + if (cpu_has_mmid) { > + write_c0_memorymapid(asid); > + write_c0_entryhi(UNIQUE_ENTRYHI(entry)); > + } else { > + write_c0_entryhi(UNIQUE_ENTRYHI(entry) | asid); > + } > + mtc0_tlbw_hazard(); > + tlb_probe(); > + tlb_probe_hazard(); > + idx =3D read_c0_index(); > + /* No match or match is on current entry */ > + if (idx < 0 || idx =3D=3D entry) > + break; > + /* > + * If we hit a match, we need to try again with > + * a different ASID. > + */ > + asid++; > + } while (asid < asid_mask); > + > + if (idx >=3D 0 && idx !=3D entry) > + panic("Unable to uniquify TLB entry %d", idx); > + > + write_c0_index(entry); > + mtc0_tlbw_hazard(); > + tlb_write_indexed(); > + entry++; > + } > + > + tlbw_use_hazard(); > + htw_start(); > + flush_micro_tlb(); > +} > + > /* > * Configure TLB (for init or after a CPU has been powered off). > */ > @@ -547,7 +601,7 @@ static void r4k_tlb_configure(void) > temp_tlb_entry =3D current_cpu_data.tlbsize - 1; >=20 > /* From this point on the ARC firmware is dead. */ > - local_flush_tlb_all(); > + r4k_tlb_uniquify(); >=20 > /* Did I tell you that ARC SUCKS? */ > } > > --- > base-commit: 911483b25612c8bc32a706ba940738cc43299496 > change-id: 20250605-tlb-fix-578bac7be546 > > Best regards, > --=20 > Jiaxun Yang --=20 - Jiaxun