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Fri, 04 Oct 2024 09:31:38 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4949VauM016682 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 4 Oct 2024 09:31:36 GMT Received: from [10.217.216.152] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 4 Oct 2024 02:31:28 -0700 Message-ID: <7ebe76e5-ed89-4ebd-bf3d-6b130b79c811@quicinc.com> Date: Fri, 4 Oct 2024 15:01:25 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 5/8] dt-bindings: clock: qcom: Add SA8775P display clock controllers From: Taniya Das To: Krzysztof Kozlowski CC: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , "Bartosz Golaszewski" , , , , , , References: <20240816-sa8775p-mm-v3-v1-0-77d53c3c0cef@quicinc.com> <20240816-sa8775p-mm-v3-v1-5-77d53c3c0cef@quicinc.com> <5kaz5wcvxhjtny5yy5i2e63ylzpor74lknvtvdkgpygxkf7yim@m6p5zof755lp> <65d129b5-088e-4cdb-a2fa-62448cfd2ad6@kernel.org> <52d2ee37-5a83-4ca2-902c-8e48b63b93b3@quicinc.com> Content-Language: en-US In-Reply-To: <52d2ee37-5a83-4ca2-902c-8e48b63b93b3@quicinc.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: UK1e4zrFCPIwI3Bls8PaozyQQOHNmD1x X-Proofpoint-ORIG-GUID: UK1e4zrFCPIwI3Bls8PaozyQQOHNmD1x X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 phishscore=0 mlxlogscore=999 mlxscore=0 adultscore=0 bulkscore=0 priorityscore=1501 clxscore=1011 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410040068 On 9/13/2024 10:35 AM, Taniya Das wrote: > > > On 9/6/2024 5:54 PM, Krzysztof Kozlowski wrote: >> On 18/08/2024 20:02, Krzysztof Kozlowski wrote: >>> On Fri, Aug 16, 2024 at 12:01:47PM +0530, Taniya Das wrote: >>>> Add device tree bindings for the display clock controllers >>>> on Qualcomm SA8775P platform. >>>> >>>> Signed-off-by: Taniya Das >>>> --- >>>>   .../bindings/clock/qcom,sa8775p-dispcc.yaml        | 79 >>>> ++++++++++++++++++++ >>>>   include/dt-bindings/clock/qcom,sa8775p-dispcc.h    | 87 >>>> ++++++++++++++++++++++ >>>>   2 files changed, 166 insertions(+) >>>> >>> >>> Reviewed-by: Krzysztof Kozlowski >> >> Un-reviewed. >> >> We achieved consensus allowing sa8775p to stay, but now Qualcomm changes >> point of view and insists on new approach of dropping sa8775p. Therefore >> this change does not make much sense in the new approach. >> > > Krzysztof could you please re-review the patches again? As I understand > that Qualcomm will support both SA8775p and QCS9100 in Kernel. There’s > no plan to drop SA8775p support. These two SoCs will keep compatible. > Krzysztof, Could you please help reviewing the patches again? -- Thanks & Regards, Taniya Das.