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[88.156.142.67]) by smtp.gmail.com with ESMTPSA id w10-20020ac2598a000000b004b4ea0f4e7fsm1043826lfn.299.2022.12.02.07.32.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 02 Dec 2022 07:32:13 -0800 (PST) Message-ID: <7ef76a8b-c45b-2a94-d0ad-9136757af684@linaro.org> Date: Fri, 2 Dec 2022 16:32:12 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.5.0 Subject: Re: [RFT PATCH v2 2/2] arm64: dts: qcom: sdm845: align TLMM pin configuration with DT schema Content-Language: en-US To: Doug Anderson Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Fritz Koenig References: <20221118164201.321147-1-krzysztof.kozlowski@linaro.org> <20221118164201.321147-2-krzysztof.kozlowski@linaro.org> <68bcdf25-e8e3-f817-f213-efb0bce3f43a@linaro.org> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 02/12/2022 15:36, Doug Anderson wrote: > Hi, > > On Fri, Dec 2, 2022 at 12:15 AM Krzysztof Kozlowski > wrote: >> >>>> qup_uart6_4pin: qup-uart6-4pin-state { >>>> - >>>> - cts-pins { >>>> + qup_uart6_4pin_cts: cts-pins { >>>> pins = "gpio45"; >>>> function = "qup6"; >>>> - bias-pull-down; >>> >>> After your patch, where is the above bias set for cheza, db845c, >>> oneplus, shift-axolotl, ...? >>> >>> >>>> }; >>>> >>>> - rts-tx-pins { >>>> + qup_uart6_4pin_rts_tx: rts-tx-pins { >>>> pins = "gpio46", "gpio47"; >>>> function = "qup6"; >>>> - drive-strength = <2>; >>>> - bias-disable; >>> >>> After your patch, where is the above bias / drive-strength set? >> >> They don't use 4-pin setup. If they use, I would assume they will >> override the entries just like sdm850 boards (where I override it to set >> these). >> >> Alternatively I can keep it in DTSI, but it is not really property of >> the SoC. > > I see things like: > > .../sdm845-cheza.dtsi: pinctrl-0 = <&qup_uart6_4pin>; > > ...before your patch that would get the bias/drive strength from the > SoC dtsi, right? After your patch, you've removed it from the dtsi but > not added it to the board. ...so I think it's a net change. Did I mess > up / miss something? I missed something or rather my git grep failed. I'll bring them back to DTSI. Best regards, Krzysztof