From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8574B30F52B for ; Mon, 6 Jul 2026 13:34:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783344897; cv=none; b=tJEtyouTNc5DfX87DwuF1WMAzhfdRFVAWy0hP0IpywBwlO8lebncfNvYfhuBQhsvjEvY5RZL1QcT0xDTGLMBjs+mmBxNTp154pCf6tA4NHT3vElgNPw/lr3Lyqs0gTXEfCRgyeeqeRMCZNxUjmpl+AcwIzKueRq9Aw4IvPwXUsU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783344897; c=relaxed/simple; bh=VyHPLux82Rci3c+vTXx+cTmtDCScjcUWQV8D3CLeEWw=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=dHUxz/Vm/NPgax4G24fHqZURaNYAZfyBmgNr7zBUwmQNd7HOe2MdI86J8jdE0c7lbTdgDiHWXbcW6DtTVr0o2OAtxM46db1cEsI2wBs6Lr6vSW4RI2LXOg+Ss6SkPVQf81zB9l8QHiv4N4fa9cwi0aaIRQ98ox/HPqaONkBmUYw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=Q0+BgtDP; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="Q0+BgtDP" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7D1CB2BCB; Mon, 6 Jul 2026 06:34:50 -0700 (PDT) Received: from [10.2.212.8] (e134344.arm.com [10.2.212.8]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D2FC43F7B4; Mon, 6 Jul 2026 06:34:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1783344894; bh=VyHPLux82Rci3c+vTXx+cTmtDCScjcUWQV8D3CLeEWw=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=Q0+BgtDP9dWJYHe6oO4gick6tJiBot33ghJdx+VvYpT6IygxKwb5+BUIR4qr+fMYF JItlX30Uz2BW9OqeEE7WiXgVKuCsvBniGYayF0ZXCJskMI61bsu14AzQ271JOdpK1J a4HXf54jmzLrZUIoJZHcfaECF0FrjBq3Ffpmb9N0= Message-ID: <7f360e5d-fe43-4c85-a501-58db5a7dabcb@arm.com> Date: Mon, 6 Jul 2026 14:34:49 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Thunderbird Daily Subject: Re: [PATCH v4 5/5] arm64: mpam: Add memory bandwidth usage (MBWU) documentation To: Fenghua Yu , Reinette Chatre Cc: amitsinght@marvell.com, baisheng.gao@unisoc.com, baolin.wang@linux.alibaba.com, carl@os.amperecomputing.com, dave.martin@arm.com, david@kernel.org, dfustini@baylibre.com, gshan@redhat.com, james.morse@arm.com, jic23@kernel.org, kobak@nvidia.com, lcherian@marvell.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, peternewman@google.com, punit.agrawal@oss.qualcomm.com, quic_jiles@quicinc.com, rohit.mathew@arm.com, scott@os.amperecomputing.com, sdonthineni@nvidia.com, tan.shaopeng@fujitsu.com, xhao@linux.alibaba.com, zengheng4@huawei.com, x86@kernel.org References: <20260520212458.1797221-1-ben.horgan@arm.com> <20260520212458.1797221-6-ben.horgan@arm.com> <4b0552cc-85cc-40b6-ab65-6b7620149f74@intel.com> <0ebb1365-9883-4974-9e8f-05c2eaa01fb1@arm.com> <5bba66e2-f671-4bdb-a2e5-f2cf9fb1f9f4@arm.com> Content-Language: en-US From: Ben Horgan In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hi Fenghua, On 7/2/26 16:46, Fenghua Yu wrote: > Hi, Ben, > > On 7/2/26 07:58, Ben Horgan wrote: >> Hi Reinette, >> >> On 7/2/26 15:46, Reinette Chatre wrote: >>> Hi Ben, >>> >>> On 7/2/26 2:20 AM, Ben Horgan wrote: >>>> On 7/1/26 23:38, Reinette Chatre wrote: >>>>> On 5/20/26 2:24 PM, Ben Horgan wrote: >>> >>> ... >>> >>>>>> --- a/Documentation/arch/arm64/mpam.rst >>>>>> +++ b/Documentation/arch/arm64/mpam.rst >>>>>> @@ -65,6 +65,23 @@ The supported features are: >>>>>>     there is at least one CSU monitor on each MSC that makes up >>>>>> the L3 group. >>>>>>     Exposing CSU counters from other caches or devices is not >>>>>> supported. >>>>>>   +* Memory Bandwidth Usage (MBWU) on or after the L3 cache.  >>>>>> resctrl uses the >>>>>> +  L3 cache-id to identify where the memory bandwidth is measured. >>>>>> For this >>>>>> +  reason the platform must have an L3 cache with cache-id's >>>>>> supplied by >>>>>> +  firmware. (It doesn't need to support MPAM.) > > s/It/The platform/? ok > >>>>>> + >>>>>> +  Memory bandwidth monitoring makes use of MBWU monitors in each >>>>>> MSC that >>>>>> +  makes up the L3 group. If the memory bandwidth monitoring is on >>>>>> the memory >>>>>> +  rather than the L3 then there must be a single global L3 as >>>>>> otherwise it > > s/a single global L3/a single global L3 cache id/? "a single global L3" seems better to me. This is just saying that the L3 is or appears to be a single L3 cache. A consequence of which is that it will have a single cache id. > >>>>>> +  is unknown which L3 the traffic came from. >>>>>> + >>>>>> +  To expose 'mbm_total_bytes', the topology of the group of MSC >>>>>> chosen must >>>>>> +  match the topology of the L3 cache so that the cache-id's can be >>>>>> +  repainted. For example: Platforms with Memory bandwidth >>>>>> monitors on >>>>>> +  CPU-less NUMA nodes cannot expose 'mbm_total_bytes' as these >>>>>> nodes do not >>>>>> +  have a corresponding L3 cache. 'mbm_local_bytes' is not exposed >>>>>> as MPAM > > Maybe remove the CPU-less example here since you will add CPU-less info > later? > > The CPU-less patches will update this document accordingly. I think this can stay until then. It is mentioned after this that the restrictions are not fundamental. Thanks, Ben > >>>>>> +  cannot distinguish local traffic from global traffic. >>>>> >>>>> Hopefully we can get to a point where memory bandwidth monitoring >>>>> data from >>>>> CPU-less NUMA nodes can be exposed via resctrl. When considering >>>>> such possible >>>> >>>> Thank you for your interest here. I hope so too. >>>> >>>>> future I think it may make this work easier to build on if the >>>>> documentation >>>>> focuses on what the current implementation supports and leave room for >>>>> future enhancements by not constraining user space expectation with >>>>> an absolute >>>>> like "CPU-less NUMA nodes cannot expose 'mbm_total_bytes'". >>>> >>>> The intention was to describe the current limitations but I do see how >>>> this can come across as fundamental problems rather than just that we >>>> need to do some more work to establish how this can be done and >>>> implement it. >>>> >>>> How about if I add this paragraph at the end? >>>> >>>> All these restrictions based on L3 cache are due to resctrl, currently, >>>> only supporting monitoring at the scope of the L3 scope. It is expected >>> >>> How about "at L3 scope" instead of "at the scope of the L3 scope"? >> >> Sure, that reads better. >> >> Ben >> >>> >>>> that going forward more MBWU monitors can be exposed to the user after >>>> support for more monitoring scopes is added to resctrl. >>> Looks good to me, thank you. >>> >>> Reinette >> > Thanks. > > -Fenghua