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Wed, 21 Oct 2026 01:42:55 -0700 (PDT) Received: from [192.168.226.26] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6b402f2c2dfsm608020a12.1.2026.10.21.01.42.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 21 Oct 2026 01:42:54 -0700 (PDT) Message-ID: <7f3a33a2-8194-4d6a-8459-73371bbf1b16@oss.qualcomm.com> Date: Wed, 21 Oct 2026 10:42:51 +0200 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 09/12] drm/msm/a8xx: devcoredump state capture support To: Rob Clark , dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich , Jie Zhang , Akhil P Oommen , Bhaskar Reddy Valluru , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Konrad Dybcio , open list References: <20261020204728.28844-1-robin.clark@oss.qualcomm.com> <20261020204728.28844-10-robin.clark@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20261020204728.28844-10-robin.clark@oss.qualcomm.com> Content-Type: text/plain; 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Such as > re-using function names, etc. > > Signed-off-by: Rob Clark > Co-developed-by: Akhil P Oommen > Signed-off-by: Rob Clark > --- [...] > +#if defined(CONFIG_DRM_MSM_GPU_STATE) > + .show = a8xx_show, > +#endif > .gpu_busy = a8xx_gpu_busy, > .gpu_get_freq = a6xx_gmu_get_freq, > .gpu_set_freq = a6xx_gpu_set_freq, > +#if defined(CONFIG_DRM_MSM_GPU_STATE) > + .gpu_state_get = a8xx_gpu_state_get, > + .gpu_state_put = a8xx_gpu_state_put, > +#endif It's odd to have 2 identical compile bounds side by side, I'd just group them [...] > +static void gen8_cx_dbgc_debugbus_select(struct msm_gpu *gpu, u32 block_id, u32 index) > +{ > + u32 reg; > + > + reg = A7XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(index) | > + A7XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(block_id); > + > + gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_A, reg); > + gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_B, reg); > + gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_C, reg); > + gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_D, reg); > + > + /* Wait 1 us to make sure the data is flowing */ > + udelay(1); Should that be a readback instead? Konrad