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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ad52d04af2asm1832533966b.4.2025.05.27.03.50.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 27 May 2025 03:50:24 -0700 (PDT) Message-ID: <7f525932-570e-4c81-a3f2-6d2e26b02233@oss.qualcomm.com> Date: Tue, 27 May 2025 12:50:21 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 5/5] phy: qcom: qmp-pcie: add x1e80100 qref supplies To: Johan Hovold , Konrad Dybcio Cc: Qiang Yu , Wenbin Yao , catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, vkoul@kernel.org, kishon@kernel.org, sfr@canb.auug.org.au, linux-phy@lists.infradead.org, krishna.chundru@oss.qualcomm.com, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, quic_cang@quicinc.com, Johan Hovold , Abel Vesa References: <20250508081514.3227956-1-quic_wenbyao@quicinc.com> <20250508081514.3227956-6-quic_wenbyao@quicinc.com> <5fd4abe7-3621-4119-9482-de823b247b0d@quicinc.com> <55a85622-fe33-4b5f-81b2-4a4270fab680@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=WfoMa1hX c=1 sm=1 tr=0 ts=683598f3 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=VwQbUJbxAAAA:8 a=zitRP-D0AAAA:8 a=4PHQb4W1jccdVsicM3wA:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 a=xwnAI6pc5liRhupp6brZ:22 X-Proofpoint-GUID: pO0kNSvT6_tHGShKnVq-2QrJ7Gf5-Zxt X-Proofpoint-ORIG-GUID: pO0kNSvT6_tHGShKnVq-2QrJ7Gf5-Zxt X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTI3MDA4OSBTYWx0ZWRfX69WFxaHH2fMd xe/ATvzGD4FYkEkCjIQdl4JlD7QA4lG5KGnBLy6MbSnFKx9CdQtJfXJ8Wt41VfnRagPLr+lkqDE 4X2K3gaTUkyrctBb0QSCrxTNmbBq7u+F16M/GEq91xUqj2SI3uKVgBPaz1ZI/qpCFj0xJuHL+Ao ZuO68LS8yHuY6Fz5aK7zhjjwfrQuAXqH9G4TRDNqxiyUqsG1hcuo/Ua7I4ArhYtRyOTWkKsP15r iIFI9vl8NvDSxzOqnvOgsNH4r6xSjJ1aIsHkuj3vJRskSkOSH2QBezdXbXIftJtYD13kL9IF1wA aVc85pdRoROvDol8eqij4xx4DJy1FU+Nmdma1/0WTV15bvWXTNC3gGXZWNuxoJsHy6WsDlUdO6q eiSk04RPU1jjypDdPBh6X9OXsicr0rjostSOmJj4eivQbc0DjfCBMeD1C5k6SRyt5TGc+px5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-27_05,2025-05-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 mlxlogscore=999 priorityscore=1501 mlxscore=0 bulkscore=0 adultscore=0 spamscore=0 suspectscore=0 malwarescore=0 clxscore=1015 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505270089 On 5/26/25 3:47 PM, Johan Hovold wrote: > On Thu, May 22, 2025 at 10:03:18PM +0200, Konrad Dybcio wrote: >> On 5/8/25 11:45 AM, Johan Hovold wrote: >>> On Thu, May 08, 2025 at 04:50:30PM +0800, Qiang Yu wrote: >>>> On 5/8/2025 4:20 PM, Johan Hovold wrote: > >>>>> This still looks wrong and you never replied to why these supplies >>>>> shouldn't be handled by the tcsr clock driver that supplies these >>>>> clocks: >>>>> >>>>> https://lore.kernel.org/lkml/aBHUmXx6N72_sCH9@hovoldconsulting.com/ >>> >>>> Sorry, I thought Konrad had convinced you. >>> >>> IIRC, he just said you guys were told to add the QREF supply to the PHY. >>> That's not an argument. >>> >>>> If the TCSR driver manages these supplies, would it be possible for tscr >>>> driver to recognize when it needs to turn vdda-qref on or off for a >>>> specific PCIe port? >>> >>> Sure, just add a lookup table to the driver and enable the required >>> supplies when a ref clock is enabled. >>> >>> As I mentioned in the other thread, the T14s has the following QREF >>> supplies: >>> >>> >>> VDD_A_QREFS_1P2_A >>> VDD_A_QREFS_1P2_B >>> >>> VDD_A_QREFS_0P875_A >>> VDD_A_QREFS_0P875_B >>> VDD_A_QREFS_0P875_0 >>> VDD_A_QREFS_0P875_2 >>> VDD_A_QREFS_0P875_3 >>> >>> and it's not clear how these maps to the various consumer ref clocks, >>> including the PCIe ones: >>> >>> #define TCSR_PCIE_2L_4_CLKREF_EN >>> #define TCSR_PCIE_2L_5_CLKREF_EN >>> #define TCSR_PCIE_8L_CLKREF_EN >>> #define TCSR_PCIE_4L_CLKREF_EN >>> >>> That mapping can be done by the TCSR clock driver (which would also take >>> care of the 1.2 V supplies). >> >> So we had an internal discussion about this and while it may work, it >> would only do so for some SoCs, and maybe only on the surface, as the >> wiring behind it is rather peculiar.. > > Care to expand on why it cannot be made to work generally? "-ENODATA".. many connections are difficult to unambiguously decipher > > Also, what would the mapping of the above QREF supplies to PCIe PHYs > even look like? I'm not sure I have a clear answer.. > >> Plus, not all QREF consumers have a clock expressed in TCSR as of >> right now. > > Is that because there is no corresponding bit in the TCSR or simply > because it has not been described yet? Unfortunately, the former.. Some IPs have a non-TCSR ref clock and some are presumably implicitly fed by BI_TCXO Konrad