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Tue, 13 Oct 2026 04:49:32 -0700 (PDT) X-Received: by 2002:a05:6a00:7615:b0:897:dda6:ad35 with SMTP id d2e1a72fcca58-897dda6b684mr8132066b3a.41.1791892172464; Tue, 13 Oct 2026 04:49:32 -0700 (PDT) Received: from [10.217.216.70] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-896c3106de6sm4969602b3a.14.2026.10.13.04.49.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 13 Oct 2026 04:49:32 -0700 (PDT) Message-ID: <7f6839fb-59b0-4f6d-a3f8-7579f6d40857@oss.qualcomm.com> Date: Tue, 13 Oct 2026 17:19:15 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/6] dt-bindings: ptp: Document the TSCSS on Qualcomm Lemans and Monaco SoCs To: Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Bjorn Andersson , Konrad Dybcio Cc: Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org References: <20260727-tscss-v1-0-beed14e72510@oss.qualcomm.com> <20260727-tscss-v1-1-beed14e72510@oss.qualcomm.com> <02792987-7ad8-4a6b-81ad-559c63174bb0@kernel.org> <640acacb-1704-4ee6-aa34-d6be3b30b44b@oss.qualcomm.com> Content-Language: en-US From: Imran Shaik In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDEzMDA0NiBTYWx0ZWRfXyp2/UD5AMamO cP9FE6T4B7cOw7lTjKjSj/NenIMXDdqmwrCjLob7qX9JMMD2O1d26oMvicECte1l5+PG5Z4TbNy ULVwhQHTcRgmQO1mBFVuNWoPcObe8KcamKEHjeEhvHgwbKY5zaUiKAvItjo8B5QOXiib3rLKwwp +H6OMqpxEpHnnvr1F1jvhOwZa+LIrOyf+fG1ToiPZTpkOQRT2ODO3a1OlT3IodLTe6MIAQUI4jG WD25BGp+VCwdesBm79PMiS7dHtbLWwUr4IFlOEIMEDoskm5lJ16+8s63aWAAaC3QznHx0mIl6iO sNPOUNH4PwidXUJxVQJbvDziJMhtnj7Qu2PraNFOdxsSXfyyQjIpOcsnhLNAFNoMCptsJgAEXIg tnjHSsRehzJG1ACxm9qkiLJg5542mcQr+kBBrVTBWi2EMJ+UMdAoLvCdUp/9/JxQtHGVVyaEkkU DpniCFD2RxWgB4/sebQ== X-Proofpoint-Spam-Info: AW1haW4tMjYxMDEzMDA0NiBTYWx0ZWRfX+2Yrqn6YzDO6 B6J0ywgHqd8MB5iLFVXfL9MfE84SNM1MC69NyYM9tbevEkQ+bsl9cTzwQgxkI31Cj6ZjJBGfUi8 0zCZIg/M630YavS9AcqJSpN1guT2VRI= X-Proofpoint-ORIG-GUID: Pe8ZbCMA5_U5SZmBfXr-7jJ-l0kQeRnT X-Authority-Analysis: v=2.4 cv=EP+TQFZC c=1 sm=1 tr=0 ts=6ace1ace cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=L7LEkksTssx7nc12Xf0A:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-GUID: Pe8ZbCMA5_U5SZmBfXr-7jJ-l0kQeRnT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-13_01,2026-10-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 phishscore=0 clxscore=1015 spamscore=0 malwarescore=0 priorityscore=1501 bulkscore=0 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610130046 On 01-09-2026 12:10 pm, Krzysztof Kozlowski wrote: > On 01/09/2026 08:31, Imran Shaik wrote: >>> >>>> + clocks: >>>> + minItems: 2 >>>> + items: >>>> + - description: TSC AHB configuration clock. >>>> + - description: TSC global counter clock. >>>> + - description: TSC ETU clock. >>>> + >>>> + clock-names: >>>> + minItems: 2 >>> >>> Why is this flexible? >>> >> >> Actually, the TSC block can standalone work without the ETU support as >> well. This ETU clock is require only when we add the ETU slice sub >> nodes. Hence, keeping the minItems to 2, excluding the ETU clock. > > Hardware either has them or not. Whether they are necessary to > prepared/enabled is independent thing and job for the driver. > Sure, will drop that flexible logic. > >> >>>> + items: >>>> + - const: ahb >>>> + - const: cntr >>>> + - const: etu >>>> + >>>> + interrupts: >>>> + description: Summary interrupt raised based on external event for any of the ETU slices. >>> >>> Please follow Linux coding style. >>> >> >> Sure, will update. >> >>>> + maxItems: 1 >>>> + >>>> + interrupt-names: >>>> + items: >>>> + - const: etu_summary >>>> + >>>> + assigned-clocks: true >>>> + assigned-clock-rates: true >>> >>> Drop. From where did you take it? >>> >> >> Actually, we need these properties to be present in the DTS to take care >> of the clock rate requirements. >> >> Please suggest on how to handle such requirements. > > Why does this binding has to be different than ALL other bindings in the > kernel? I am not talking about DTS now. > Sure, will check and drop. >> >>>> + >>>> + "#address-cells": >>>> + const: 2 >>>> + >>>> + "#size-cells": >>>> + const: 2 >>>> + >>>> + ranges: true >>>> + >>>> +patternProperties: >>>> + "^etu-slice@[0-9a-f]+$": >>>> + type: object >>>> + description: ETU slice configuration >>>> + properties: >>>> + reg: >>>> + maxItems: 1 >>>> + >>>> + pinctrl-0: true >>>> + >>>> + pinctrl-names: >>>> + items: >>>> + - const: default >>> >>> Heh? Which code do you copy? >>> >> >> Each ETU slice has its own external event pin config, so kept pinctrl-0 >> and pinctrl-names on the slice subnode. Please suggest if you prefer >> otherwise. > > No, from where did you get this code? Why are you sending bindings which > are different then all other bindings? > I was referring to the example in [1] when adding the pinctrl properties under the etu-slice sub node. [1] - Documentation/devicetree/bindings/media/samsung,exynos4212-fimc-is.yaml On checking further, I found that our etu-slice sub node deviates from that example, since we don't have a compatible string for the sub node. Please let me know if we should move the pinctrl properties under the tscss node with per-slice names, or instead keep them under the etu-slice sub node and add a compatible there. > >> >>>> + >>>> + qcom,etu-event-sel: >>>> + description: Event selection value for this slice. >>>> + $ref: /schemas/types.yaml#/definitions/uint32 >>>> + >>>> + qcom,etu-slice: >>>> + description: ETU slice identifier. >>> >>> You do not get identifiers. Please read writing bindings. >>> >> >> In general, any ETU slice can function with any ETU event sel, and this >> might not be 1-1 always. Also, these ETU slices can be configured by the >> vendors based on the requirements of the GPIOs on the board. Hence, this >> etu-slice identifier will provide the flexibility to configure >> accordingly. > > 'reg' defines which ETU slice is this, no? > Yes, will drop qcom,etu-slice property. > > Best regards, > Krzysztof