From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755678AbeCSPSY convert rfc822-to-8bit (ORCPT ); Mon, 19 Mar 2018 11:18:24 -0400 Received: from smtp-out4.electric.net ([192.162.216.185]:55469 "EHLO smtp-out4.electric.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755417AbeCSPSU (ORCPT ); Mon, 19 Mar 2018 11:18:20 -0400 From: David Laight To: "'Thomas Gleixner'" CC: "'Rahul Lakkireddy'" , "x86@kernel.org" , "linux-kernel@vger.kernel.org" , "netdev@vger.kernel.org" , "mingo@redhat.com" , "hpa@zytor.com" , "davem@davemloft.net" , "akpm@linux-foundation.org" , "torvalds@linux-foundation.org" , "ganeshgr@chelsio.com" , "nirranjan@chelsio.com" , "indranil@chelsio.com" Subject: RE: [RFC PATCH 0/3] kernel: add support for 256-bit IO access Thread-Topic: [RFC PATCH 0/3] kernel: add support for 256-bit IO access Thread-Index: AQHTv43TjMVMzNQoikSg1VH837bpVaPXnqXggAAJp4CAAAH+gA== Date: Mon, 19 Mar 2018 15:19:01 +0000 Message-ID: <7f8d811e79284a78a763f4852984eb3f@AcuMS.aculab.com> References: <7f0ddb3678814c7bab180714437795e0@AcuMS.aculab.com> In-Reply-To: Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.202.205.33] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-Outbound-IP: 156.67.243.126 X-Env-From: David.Laight@ACULAB.COM X-Proto: esmtps X-Revdns: X-HELO: AcuMS.aculab.com X-TLS: TLSv1.2:ECDHE-RSA-AES256-SHA384:256 X-Authenticated_ID: X-PolicySMART: 3396946, 3397078 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Thomas Gleixner > Sent: 19 March 2018 15:05 > > On Mon, 19 Mar 2018, David Laight wrote: > > From: Rahul Lakkireddy > > In principle it ought to be possible to get access to one or two > > (eg) AVX registers by saving them to stack and telling the fpu > > save code where you've put them. > > No. We have functions for this and we are not adding new ad hoc magic. I was thinking that a real API might do this... Useful also for code that needs AVX-like registers to do things like CRCs. > > OTOH, for x86, if the code always runs in process context (eg from a > > system call) then, since the ABI defines them all as caller-saved > > the AVX(2) registers, it is only necessary to ensure that the current > > FPU registers belong to the current process once. > > The registers can be set to zero by an 'invalidate' instruction on > > system call entry (hope this is done) and after use. > > Why would a system call touch the FPU registers? The kernel normally does > not use FPU instructions and the code which explicitely does has to take > care of save/restore. It would be performance madness to fiddle with the > FPU stuff unconditionally if nothing uses it. If system call entry reset the AVX registers then any FP save/restore would be faster because the AVX registers wouldn't need to be saved (and the cpu won't save them). I believe the instruction to reset the AVX registers is fast. The AVX registers only ever need saving if the process enters the kernel through an interrupt. David