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Tue, 21 Jul 2026 08:07:11 -0700 (PDT) X-Received: by 2002:a05:6102:3e0a:b0:739:cbf7:93dd with SMTP id ada2fe7eead31-74abc8c54c1mr637416137.6.1784646431492; Tue, 21 Jul 2026 08:07:11 -0700 (PDT) Received: from [192.168.120.193] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c1712a5f8c5sm610446866b.34.2026.07.21.08.07.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 21 Jul 2026 08:07:10 -0700 (PDT) Message-ID: <7fa30af8-884f-4302-ba88-92720bc741eb@oss.qualcomm.com> Date: Tue, 21 Jul 2026 17:07:08 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/3] i2c: qcom-cci: Fix CCI clock rate enforcement To: Loic Poulain , Robert Foss , Andi Shyti , Wolfram Sang , Dmitry Baryshkov , Luca Weiss Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260721-cci-clk-fix-v1-0-5eae78700da8@oss.qualcomm.com> <20260721-cci-clk-fix-v1-3-5eae78700da8@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260721-cci-clk-fix-v1-3-5eae78700da8@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: z85gsly_qvvvThPraAGowZ3ICNtbz3Rg X-Authority-Analysis: v=2.4 cv=TIZ1jVla c=1 sm=1 tr=0 ts=6a5f8b20 cx=c_pps a=KB4UBwrhAZV1kjiGHFQexw==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=Qs5JWBi5AS5GbOw7t0EA:9 a=QEXdDO2ut3YA:10 a=o1xkdb1NAhiiM49bd1HK:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIxMDE2MCBTYWx0ZWRfX6YNOpS0FHQYW UemQyAdZPVVRodhEeRyNRiI8pzmcnvzdgbrzGiyocI6oGAaSPZu8lySCrLzKWS0ymRMzv6fg7yi /T8HjiBldmuZN05iIvRSEy/wHIXTDQA= X-Proofpoint-GUID: z85gsly_qvvvThPraAGowZ3ICNtbz3Rg X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIxMDE2MCBTYWx0ZWRfX/789HDTK7bVZ ujKHtUNXdWYTXLcOTQd5E7yO9GajNHVdeH6y6Cv+YWKZLriWoa6xAjt5w4+YIbQlMtCfEkXqlkK KF4DP41qHmqqJPjmqY2FoHrnT9THmvZCUWuGuK+2iFHbB2u1tHOUJiIC0hHZ7GQIjsyeA4sOAyc Mn/4vJVJ13sGsr1V5gmQd1oPcAOeXS+9Z9G2VOaZNJRLPG785FX9VLA1nBf1BFOjbzyXYewZyeM m/AIc5eniwOe/8nnUqG7oUhB6fcJ8tevfYzelsy7kCxzYPQyp9qEk5EqzMADPvLfajNjnaCMEIT Lv4DCcGkvXHTk0QZ5/LhhFFRpV5JkmC+yWWLiP3CBz53kcTj1plCCLVf8nJKhBuPmwaGG+l0IAA 6F/nNY8RsYOrF5qrriFfyRuEXp1Wh6UinfYfdbJxC7RxxPR0SYC/8581r8NgDHHsq7V80MFY9la VSS+Jm1ZnrSSggQLP0A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-21_03,2026-07-20_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 priorityscore=1501 spamscore=0 clxscore=1015 malwarescore=0 bulkscore=0 suspectscore=0 adultscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607210160 On 7/21/26 4:58 PM, Loic Poulain wrote: > The hw_params timing values (thigh, tlow, etc.) are in CCI clock ticks > and were calibrated for a specific clock rate per hardware variant. If > the clock is running at a different rate the I2C timings will be wrong, > potentially violating the I2C specification. > > Rather than just warning about a mismatch, actively set the clock to the > expected rate at probe time. Warn if the rate could not be applied so the > user is informed that timings may be incorrect. > > Signed-off-by: Loic Poulain > --- > drivers/i2c/busses/i2c-qcom-cci.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/i2c/busses/i2c-qcom-cci.c b/drivers/i2c/busses/i2c-qcom-cci.c > index 5f74edde8558382e63e2c3d0fbe19489f325e8ce..e001c0d565cebd386fd67b1d9d532360b29c67d0 100644 > --- a/drivers/i2c/busses/i2c-qcom-cci.c > +++ b/drivers/i2c/busses/i2c-qcom-cci.c > @@ -519,6 +519,7 @@ static int cci_probe(struct platform_device *pdev) > struct device *dev = &pdev->dev; > struct device_node *child; > struct resource *r; > + struct clk *cci_clk; > struct cci *cci; > int ret, i; > u32 val; > @@ -587,6 +588,15 @@ static int cci_probe(struct platform_device *pdev) > return dev_err_probe(dev, -EINVAL, "not enough clocks in DT\n"); > cci->nclocks = ret; > > + cci_clk = devm_clk_get(dev, "cci"); > + if (IS_ERR(cci_clk)) > + return dev_err_probe(dev, PTR_ERR(cci_clk), "failed to get CCI clock\n"); > + > + clk_set_rate(cci_clk, cci->data->cci_clk_rate); > + if (clk_get_rate(cci_clk) != cci->data->cci_clk_rate) > + dev_warn(dev, "CCI clock is not at expected %lu Hz\n", > + cci->data->cci_clk_rate); This needs to go through OPP. Feel free to take over and refresh: https://lore.kernel.org/linux-arm-msm/20250904-topic-cci_updates-v1-0-d38559692703@oss.qualcomm.com/ Konrad