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Mon, 22 May 2023 18:03:12 GMT Received: from [10.71.110.193] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Mon, 22 May 2023 11:03:11 -0700 Message-ID: <7fabb62d-0483-1298-c6ce-1f37313faa67@quicinc.com> Date: Mon, 22 May 2023 11:03:11 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH v3 3/5] drm/msm/dpu: Add DPU_INTF_DATA_COMPRESS feature flag Content-Language: en-US To: Marijn Suijten CC: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Konrad Dybcio , , , , References: <20230405-add-dsc-support-v3-0-6e1d35a206b3@quicinc.com> <20230405-add-dsc-support-v3-3-6e1d35a206b3@quicinc.com> From: Jessica Zhang In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: jrr_NFTcF4EkG6O-r8WeSI6saAGRqfLu X-Proofpoint-GUID: jrr_NFTcF4EkG6O-r8WeSI6saAGRqfLu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-05-22_12,2023-05-22_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 bulkscore=0 malwarescore=0 mlxlogscore=841 suspectscore=0 adultscore=0 phishscore=0 mlxscore=0 impostorscore=0 priorityscore=1501 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305220152 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 5/19/2023 2:34 PM, Marijn Suijten wrote: > On 2023-05-19 14:17:28, Jessica Zhang wrote: >> Add DATA_COMPRESS feature flag to DPU INTF block. >> >> In DPU 7.x and later, DSC/DCE enablement registers have been moved from >> PINGPONG to INTF. >> >> Reviewed-by: Marijn Suijten >> Signed-off-by: Jessica Zhang >> --- >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +- >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++ >> 2 files changed, 3 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> index 7944481d0a33..c74051906d05 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> @@ -104,7 +104,7 @@ >> #define INTF_SC7180_MASK \ >> (BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE) | BIT(DPU_INTF_STATUS_SUPPORTED)) >> >> -#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN) >> +#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN) | BIT(DPU_INTF_DATA_COMPRESS) > > We should really wrap these in parenthesis at some point. Hi Marijn, Acked. Thanks, Jessica Zhang > >> >> #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \ >> BIT(DPU_WB_UBWC) | \ >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >> index 4eda2cc847ef..01c65f940f2a 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >> @@ -185,6 +185,7 @@ enum { >> * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate >> * than video timing >> * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register >> + * @DPU_INTF_DATA_COMPRESS INTF block has DATA_COMPRESS register >> * @DPU_INTF_MAX >> */ >> enum { >> @@ -192,6 +193,7 @@ enum { >> DPU_INTF_TE, >> DPU_DATA_HCTL_EN, >> DPU_INTF_STATUS_SUPPORTED, >> + DPU_INTF_DATA_COMPRESS, >> DPU_INTF_MAX >> }; >> >> >> -- >> 2.40.1 >>