Re: [PATCH 6/8] MIPS: Limit MIPS_MT_SMP support by ISA reversion

["Jiaxun Yang" <jiaxun.yang@flygoat.com>]

在2024年5月14日五月 下午10:38，Maciej W. Rozycki写道：
> On Fri, 2 Feb 2024, Jiaxun Yang wrote:
>
>> MIPS MT ASE is only available on ISA between Release 1 and Release 5.
>
>  R2+ only actually, as also evident from Kconfig...

Hi Maciej,

Long time no see :-)

There is nothing stopping us to run R1 kernel on R2 hardware, given that
those features are all detected at boot time. I understand MT was introduced
at 34K which is R2.

I tested booting R1 kernel with MT on 1004Kc.

I believe we should give users flexibility on enjoying optional features
on kernel targeting lower ISA Rev.

>
>> --- a/arch/mips/Kconfig
>> +++ b/arch/mips/Kconfig
>> @@ -2171,7 +2171,8 @@ config CPU_R4K_CACHE_TLB
>>  config MIPS_MT_SMP
>>  	bool "MIPS MT SMP support (1 TC on each available VPE)"
>>  	default y
>> -	depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
>> +	depends on TARGET_ISA_REV > 0 && TARGET_ISA_REV < 6
>> +	depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MICROMIPS
>>  	select CPU_MIPSR2_IRQ_VI
>>  	select CPU_MIPSR2_IRQ_EI
>                    ^^^^^^
>  ... here.  I wish people looked beyond the line they change, sigh...

Both features (VI and VEIC) are probed at boot time. Selecting
them doesn't necessarily mean that CPU has those functions.

Thanks
- Jiaxun
>
>   Maciej

-- 
- Jiaxun