Re: [PATCH v2 2/2] phy: cadence-torrent: Add PCIe + XAUI multilink configuration for 100MHz refclk

[Andrew Lunn <andrew@lunn.ch>]

On Sun, Jan 04, 2026 at 05:14:18PM +0530, Siddharth Vadapalli wrote:
> From: Swapnil Jakhade <sjakhade@cadence.com>
> 
> Add register sequences for PCIe + XAUI multilink configuration for
> 100MHz reference clock.
> 
> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
> 
> v1 of this patch is at:
> https://lore.kernel.org/r/20251224054905.763399-3-s-vadapalli@ti.com/
> No changes since v1.
> 
> Regards,
> Siddharth.
> 
>  drivers/phy/cadence/phy-cadence-torrent.c | 143 ++++++++++++++++++++--
>  1 file changed, 136 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
> index 37fa4bad6bd7..f0d870886cca 100644
> --- a/drivers/phy/cadence/phy-cadence-torrent.c
> +++ b/drivers/phy/cadence/phy-cadence-torrent.c
> @@ -300,6 +300,7 @@ enum cdns_torrent_phy_type {
>  	TYPE_USB,
>  	TYPE_USXGMII,
>  	TYPE_PCIE_ML,
> +	TYPE_XAUI,
>  };
>  
>  enum cdns_torrent_ref_clk {
> @@ -320,14 +321,14 @@ enum cdns_torrent_ssc_mode {
>  /* Unique key id for vals table entry
>   * REFCLK0_RATE | REFCLK1_RATE | LINK0_TYPE | LINK1_TYPE | SSC_TYPE
>   */
> -#define REFCLK0_SHIFT	12
> -#define REFCLK0_MASK	GENMASK(14, 12)
> -#define REFCLK1_SHIFT	9
> -#define REFCLK1_MASK	GENMASK(11, 9)
> -#define LINK0_SHIFT	6
> -#define LINK0_MASK	GENMASK(8, 6)
> +#define REFCLK0_SHIFT	15
> +#define REFCLK0_MASK	GENMASK(18, 15)
> +#define REFCLK1_SHIFT	11
> +#define REFCLK1_MASK	GENMASK(14, 11)
> +#define LINK0_SHIFT	7
> +#define LINK0_MASK	GENMASK(10, 7)

Why do these change? It would be good to add an explanation to the
commit message about this, because it is not obvious why these need to
change.

       Andrew