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The Flush should have been a no-op > to the device with WCE cleared, so something seems off here. > > I'm wondering if the device is actually really respecting WCE set to 0 > now. That might be tricky to prove, but it wouldn't be the first time a > device lied about durability. Not saying that's happening here, but the > behavior you're reporting is suspicious: 15usec writes are not > physically possible with TLC NAND (your model says BiCS TLC) without a > cache, and your controller says your cache is volatile. > > Anyway, the principle of what you're proposing looks fine to me from a > spec standpoint. I'll get this queued up if I don't see any other review > feedback or concerns that it's going to corrupt something... Thanks for your feedback. I'll discuss this firmware question with the vendor in private and will keep you aware. Considering the performance impact for these type of device,s would you be open to a backport to stable once merged ? This patch is really about matching the spec and it would be probably a great positive impact for many stable users to benefit from this patch. WDYT ? Erwan,