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Sverdlin" , CC: Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Tero Kristo , "Santosh Shilimkar" , Andrew Davis , Jayesh Choudhary , Siddharth Vadapalli , Abraham I , Roger Quadros , , References: <20260316070429.1545707-1-alexander.sverdlin@siemens.com> <20260316070429.1545707-4-alexander.sverdlin@siemens.com> From: Vignesh Raghavendra Content-Language: en-US In-Reply-To: <20260316070429.1545707-4-alexander.sverdlin@siemens.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001C9:EE_|PH0PR10MB4631:EE_ X-MS-Office365-Filtering-Correlation-Id: 20a22fb9-3507-4bb3-f2f4-08de83e8def4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|82310400026|36860700016|56012099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: ACJDDT2fzHNrm/M4yZOpJu5KgjQjJN+LrRagEUeKPWHIBPRz4rsnNwz5BXw0k+JI25hqxomZHZR1FQo3icmmlqW0uHvnv+m8viM1S1VF7BmA1m12HxqyGPIzngYf2mX729DlaovN+6PqAR82uXoizvzgKL9dL4jtTm3WlxZGphTvF6+H1T08eSVZyqRgL3gn3NNTNli51D2kvULPYVVp+UVAGnmcOU38k7P6FIkbiKlX17tvkGMHvDc95SATBXOavpa1VwqdPVLyyZX9hLaWk6WdAgNmaQA4OMu/KE8weKEgP++OSXpQWJi5vzFSUNoGMhMjN13QZD5LfQGfc/IsFzLkyh/xjMzRk2XhZ0JT67gjDd2+VXIN0nHKOLyHCvJDDSrKkiPjY2QdO0Zz0WyDk5ooajE8g9mquDNb2C6EMWduMwGIpU49kwai+vQxwFFx1aVD9aMKo24zMJG1x0SiTz1jTs7fbROjMqoIU1T0Pu8lRohoMWun/JhSAMvq62dq7kudV+iPIYqptDComMd0eI97VjDAdgD6l6OO5ikuBO1XmRqiMm71OfjZMQDR1NhP7JQHbXOqFXUWupqM1ER7A5JHeYBFEV5+ap1KifegrrCA0m6YM0Tjr4hMhZnmXk6VWBVRF93GlwP6qFTgQompSpFb5+98RlA2H7pk4yDBkCWcxxyr8EziT827KSreaP8uyoK+ebdXo7ahsyhZrf1YHxmRzgKJ75p5xe66rqoyETk= X-Forefront-Antispam-Report: CIP:198.47.23.195;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:lewvzet201.ext.ti.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(376014)(82310400026)(36860700016)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 2aXmZyFhQw1R5CeMVq3AAlgo9QxPjcUjcfNtqlee1gU6BOrYLbpv7eQK7she9Z/Zy1KTc8ltQOFWWefb5XuLHJsAdjdInSMyRk9BpLrWPM4kc8uIxj9RDZCgb7FSweGXFV19774IQjgQ3WIN38+W4PRDtamDr7HlBCAzWC+CimtOYMSFgEF3afRP8Vlk0gFqV/XBFP0V0CZTstJie5c2TKr/vZ0r+hrQiSrT+qKQ1h6QqQWQ11p4TvWgvjghgbotO3AgjAfjOWMostLgdulmezOJYPAZcODBRkMm3Z0f2PLNL33vRWEoBUx2EQ6GU6akcxDv0K8nYDA/0ViEzUG9H9F/g2htvXX5CbrQQRKUMgGwitIAbVMpjuLeJZE+qk9rWAt9qn44gcSw7DSSnrsgTtKAIipMqcjDxbXWRF1uYlHe+ETFmbVjVYNXB0d+t5O/ X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 05:48:52.7990 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 20a22fb9-3507-4bb3-f2f4-08de83e8def4 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.195];Helo=[lewvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001C9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR10MB4631 Hi, Thanks for the patch! On 16/03/26 12:34, A. Sverdlin wrote: > From: Alexander Sverdlin > > Add reset_reason attribute decoging the RST_SRC register present in AM64x s/decoging/decoding . please run spellcheck on commit msg > and later SoCs of K3 family. Textual representation of the bits was taken > from the AM62x Processors Technical Reference Manual, except the POR, which > is not signalled explicitly by the reset module. > > Signed-off-by: Alexander Sverdlin There is support dumping reset reason in U-Boot for AM64x: https://elixir.bootlin.com/u-boot/v2026.01/source/arch/arm/mach-k3/am64x/boot.c#L107 This conflicts with kernel as U-Boot currently clears the RST_SRC after read (Its necessary to do so, to detect additional resets at bootloader level). So, this information would be lost by the time kernel driver comes up. Is there a usecase where kernel can make use of reset reason information exposed via this driver? If so, the driver should at least take a cmdline param from bootloader in order to overcome above issue. > --- > Changelog: > v2: no changes > > drivers/soc/ti/k3-socinfo.c | 88 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 88 insertions(+) > > diff --git a/drivers/soc/ti/k3-socinfo.c b/drivers/soc/ti/k3-socinfo.c > index 676041879eca3..3736c982fd0c8 100644 > --- a/drivers/soc/ti/k3-socinfo.c > +++ b/drivers/soc/ti/k3-socinfo.c > @@ -45,6 +45,8 @@ > #define JTAG_ID_PARTNO_J722S 0xBBA0 > #define JTAG_ID_PARTNO_AM62LX 0xBBA7 > > +#define CTRL_MMR_RST_SRC 8 > + > static const struct k3_soc_id { > unsigned int id; > const char *family_name; > @@ -123,6 +125,90 @@ static const struct regmap_config k3_chipinfo_regmap_cfg = { > .reg_stride = 4, > }; > > +static u32 k3_reset_source; > +static const char *const k3_reset_sources[] = { > + [0] = "Reset Caused by MCU Reset Pin", > + [1] = "Power On Reset", /* Reserved in HW */ > + [2] = "Main Reset Pin", > + [4] = "Thermal Reset", > + [8] = "Debug Subsystem Initiated Reset", > + [12] = "SMS Cold Reset", > + [13] = "SMS Warm Reset", > + [16] = "Software Warm Reset", > + [20] = "Software Main Warm Reset From MCU CTRL MMR", > + [21] = "Software Main Warm Reset from MAIN CTRL MMR", > + [22] = "Watchdog Initiated Reset", > + [24] = "Software Main Power On Reset From MCU CTRL MMR", > + [25] = "Software Main Power On Reset From MAIN CTRL MMR", > + [30] = "Reset Caused by Main ESM Error", > + [31] = "Reset Caused by MCU ESM Error", > +}; > + > +static ssize_t reset_reason_show(struct device *dev, struct device_attribute *attr, char *buf) > +{ > + int ret, i; > + int total = 0; > + > + for (i = ARRAY_SIZE(k3_reset_sources); i >= 0; i--) { > + if (!k3_reset_sources[i] || !(k3_reset_source & BIT(i))) > + continue; > + > + ret = sprintf(buf + total, "%s\n", k3_reset_sources[i]); > + if (ret < 0) > + return ret; > + total += ret; > + /* Note that several reset sources may be active simultaneously */ > + } > + > + return total; > +} > + > +static DEVICE_ATTR_RO(reset_reason); > + > +static struct attribute *k3_soc_attrs[] = { > + &dev_attr_reset_reason.attr, > + NULL > +}; > + > +ATTRIBUTE_GROUPS(k3_soc); > + > +static const struct of_device_id k3_rst_id_table[] = { > + { > + .compatible = "ti,am64-rst", > + }, > + {} > +}; > + > +static void k3_reset_reason_read(struct soc_device_attribute *soc_dev_attr) > +{ > + struct device_node *node = of_find_matching_node(NULL, k3_rst_id_table); > + struct regmap *regmap; > + > + /* AM65x/J721E do not have similar registers */ > + if (!node) > + return; > + > + regmap = device_node_to_regmap(node); > + of_node_put(node); > + if (IS_ERR(regmap)) { > + pr_err("Cannot obtain %s regmap\n", k3_rst_id_table[0].compatible); > + return; > + } > + > + regmap_read(regmap, CTRL_MMR_RST_SRC, &k3_reset_source); > + /* > + * The register is only being cleared on POR, so we have to clear reset > + * source of the current boot manually > + */ > + regmap_write(regmap, CTRL_MMR_RST_SRC, k3_reset_source); > + > + /* Simplify the code a bit and use HW-reserved bit for POR indication */ > + if (!k3_reset_source) > + k3_reset_source |= BIT(1); > + > + soc_dev_attr->custom_attr_group = k3_soc_groups[0]; > +} > + > static int k3_chipinfo_probe(struct platform_device *pdev) > { > struct device_node *node = pdev->dev.of_node; > @@ -183,6 +269,8 @@ static int k3_chipinfo_probe(struct platform_device *pdev) > of_property_read_string(node, "model", &soc_dev_attr->machine); > of_node_put(node); > > + k3_reset_reason_read(soc_dev_attr); > + > soc_dev = soc_device_register(soc_dev_attr); > if (IS_ERR(soc_dev)) { > ret = PTR_ERR(soc_dev); -- Regards Vignesh https://ti.com/opensource