From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.0 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9304C28CC5 for ; Wed, 5 Jun 2019 17:37:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A270E20717 for ; Wed, 5 Jun 2019 17:37:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="UW304hnU" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726633AbfFERhA (ORCPT ); Wed, 5 Jun 2019 13:37:00 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:33347 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726421AbfFERhA (ORCPT ); Wed, 5 Jun 2019 13:37:00 -0400 Received: by mail-pf1-f194.google.com with SMTP id x15so5453172pfq.0 for ; Wed, 05 Jun 2019 10:37:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:subject:in-reply-to:references:date:message-id:mime-version; bh=/updNbVAXDRpwIEN7mxRzjn7O5DNwkaGNW0XCgNkty0=; b=UW304hnUawBvIhjTZZ77gkYQxhciqbhVs6H7uhZYjC3wM4CCIPIKUtB4itcDzxycrK XM9m8Zs/UuaeYIVybKePE1SpMQo/kOCPO3GfH8Q2OSh/sZGRpPkVrTbPdeOkm01RaGrk 3m8bMzKhpSUcDYPEz+ifQ0IIqvokUZ2iFvZaVkNDtBRlTc7UYDIfrTxqzsOdgsWd0l2Z OTTFj82yQ9s0e8zRFmhTJN+OHgv+4vSrAKkeLyEeBgF5qDhpa624FFyVmoAEGeIU0WLx 0MO7K9RbTNexgAlMJoeVD9u5aqaDWZkZF/pW3FgKn6NE0F4DwjeDOACyV3QIV1VfXOUN MxkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:in-reply-to:references:date :message-id:mime-version; bh=/updNbVAXDRpwIEN7mxRzjn7O5DNwkaGNW0XCgNkty0=; b=eylkINd16qNhgTS5upcoSkIrXqCDtosrNmgJMlZmlCEA5hnloXJzTJK0iqO+POKfQc tUDO3GKBDRxVi5yMBD3mMyrHRpPbkZSPjJ8tbTlswalk3g1PSXbxYLpZv9Q8Lj20ddM+ cHuiEYamvrfnHg74K+nFqdDD6OSK1hEws3/Aghv15ovQfw1ujm8Mbczlu3C6h4wXTIMt TVntXVlQdjYazCX0544SrZOvFOoi7fKnsn83EkFyAgXwSQsovDyCY0adDl124ioYooT9 xXVQjsiGxwDDyBQCyyZ3sjPqPbwoOlD231npEbCKZiKZNq7bXlTDOIefrK6sDiBagusC Bj4w== X-Gm-Message-State: APjAAAUf2azmDubWPuOFNqngttxGyB/WBEIhWmurN5pu9egGbkxsfk9N 2Z8V3yP4Z4mGKZEX2yngjTV7dQ== X-Google-Smtp-Source: APXvYqyk3K4EqN15Job2mwtC6F0AWmOqpL3rIbmhXdwLidwXBLjenjtBYFFXGMyDk8TJGTw6Bmkhkw== X-Received: by 2002:a63:6cc3:: with SMTP id h186mr5988401pgc.292.1559756219480; Wed, 05 Jun 2019 10:36:59 -0700 (PDT) Received: from localhost (c-71-197-186-152.hsd1.wa.comcast.net. [71.197.186.152]) by smtp.googlemail.com with ESMTPSA id u20sm10101223pga.82.2019.06.05.10.36.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 05 Jun 2019 10:36:58 -0700 (PDT) From: Kevin Hilman To: Paul Walmsley , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v3 0/5] arch: riscv: add board and SoC DT file support In-Reply-To: <20190602080500.31700-1-paul.walmsley@sifive.com> References: <20190602080500.31700-1-paul.walmsley@sifive.com> Date: Wed, 05 Jun 2019 10:36:58 -0700 Message-ID: <7h36kogchx.fsf@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Paul, Paul Walmsley writes: > Add support for building flattened DT files from DT source files under > arch/riscv/boot/dts. Follow existing kernel precedent from other SoC > architectures. Start our board support by adding initial support for > the SiFive FU540 SoC and the first development board that uses it, the > SiFive HiFive Unleashed A00. > > This third version of the patch set adds I2C data for the chip, > incorporates all remaining changes that riscv-pk was making > automatically, and addresses a comment from Rob Herring > . > > Boot-tested on v5.2-rc1 on a HiFive Unleashed A00 board, using the > BBL and open-source FSBL, with modifications to pass in the DTB > file generated by these patches. Tested this series on top of v5.2-rc3 on HiFive Unleashed board using OpenSBI + mainline u-boot (master branch as of today). Tested-by: Kevin Hilman > This patch series can be found, along with the PRCI patch set > and the DT macro prerequisite patch, at: > > https://github.com/sifive/riscv-linux/tree/dev/paulw/dts-v5.2-rc1 nit: I only see this series in that branch, not any of the prerequisite patches you mentioned, which made me assume I could this series alone on top of v5.2-rc3, which worked just fine. Kevin