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From: Kevin Hilman <khilman@baylibre.com>
To: Yixun Lan <yixun.lan@amlogic.com>
Cc: Neil Armstrong <narmstrong@baylibre.com>,
        Jerome Brunet <jbrunet@baylibre.com>, Rob Herring <robh+dt@kernel.org>,
        Mark Rutland <mark.rutland@arm.com>,
        Michael Turquette <mturquette@baylibre.com>,
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        Qiufang Dai <qiufang.dai@amlogic.com>,
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        <linux-clk@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>,
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Subject: Re: [PATCH v4 0/4] add clk controller driver for Meson-AXG SoC
Organization: BayLibre
References: <20171201012452.27086-1-yixun.lan@amlogic.com>
Date: Wed, 06 Dec 2017 11:13:59 -0800
In-Reply-To: <20171201012452.27086-1-yixun.lan@amlogic.com> (Yixun Lan's
        message of "Fri, 1 Dec 2017 09:24:48 +0800")
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Yixun Lan <yixun.lan@amlogic.com> writes:

> Add driver for the clk controller which found in Meson AXG SoC
>
>   Note, we deliberately create a seperate source file for the Meson AXG
> series, instead of sharing code with previous GXBB/GXL - the file axg.c
> It would help us maintaining the code more easily.

In addition to the DT node-name fixup (c.f. reply on v3 series), I think
this series should also include a patch that switches the UART over to
the new clock provider (it's currently using the xtal fixed clock.)

This will also provide a simple way to validate/test the series.

Kevin