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([2a02:e98:40:8091:f0f7:91a3:e60:541a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4b90619bbd2sm149230065e9.1.2026.11.09.07.37.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 09 Nov 2026 07:37:44 -0800 (PST) Message-ID: <800f8d42-e35d-47ec-bbe6-e437a86d6e70@gmail.com> Date: Mon, 9 Nov 2026 16:37:43 +0100 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] serial: 8250: Add RX trigger levels for U6_16550A To: =?UTF-8?Q?Ilpo_J=C3=A4rvinen?= Cc: Andy Shevchenko , Greg Kroah-Hartman , Jiri Slaby , Heiko Stuebner , LKML , linux-serial , linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Miroslav Ondra References: <20261109-8250-select-u6-64bit-v1-0-04bc8332fa34@gmail.com> <20261109-8250-select-u6-64bit-v1-1-04bc8332fa34@gmail.com> <469362ef-f0c5-45f2-746a-b4a3c51876a4@linux.intel.com> Content-Language: cs From: =?UTF-8?B?S3J5xaF0b2YgxIxlcm7DvQ==?= In-Reply-To: <469362ef-f0c5-45f2-746a-b4a3c51876a4@linux.intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit > On Mon, 9 Nov 2026, Kryštof Černý via B4 Relay wrote: > >> From: Kryštof Černý >> >> PORT_U6_16550A has a 64-byte FIFO but no rxtrig_bytes table, so the >> rx_trig_bytes sysfs attribute is not registered for ports of this type >> and the RX trigger level cannot be read or changed from userspace. >> >> Add a table with 1, 16, 32 and 62 bytes, i.e. 1 character, FIFO 1/4 >> full, FIFO 1/2 full and FIFO 2 less than full. These are the levels the >> Synopsys DesignWare UART uses for a 64-byte FIFO, and they match the >> existing PORT_ALTR_16550_F64 table. >> >> The default FCR value of the type is unchanged, so the trigger level a >> port starts with stays at 1/2 full. The only visible change for ports >> already detected as U6_16550A by autoconfig is the new sysfs attribute. >> >> This prepares for 8250_dw selecting PORT_U6_16550A for DesignWare UARTs >> with a 64-byte FIFO. >> >> Co-developed-by: Miroslav Ondra >> Signed-off-by: Miroslav Ondra >> Signed-off-by: Kryštof Černý >> --- >> drivers/tty/serial/8250/8250_port.c | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c >> index 36b2b0a2c05c..a7acede62f40 100644 >> --- a/drivers/tty/serial/8250/8250_port.c >> +++ b/drivers/tty/serial/8250/8250_port.c >> @@ -163,6 +163,7 @@ static const struct serial8250_config uart_config[] = { >> .fifo_size = 64, >> .tx_loadsz = 64, >> .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, >> + .rxtrig_bytes = {1, 16, 32, 62}, > > Reusing U6 entry for DW UARTs seems misleading. > > We've better mechanism coming up for defining rxtrig in a one pending > series so this constant friction with the uart config types can be put > into rest. > > Please build on top of that other series and help in testing and reviewing > it. Thanks for the information, I started the work about a month ago and not sure if the patch existed before. I will test the other series on my hardware. I like that approach more.