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Wed, 29 Nov 2023 15:46:28 GMT Received: from [10.131.33.37] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 29 Nov 2023 07:46:21 -0800 Message-ID: <8021a6f5-6316-031d-8181-e0e2047e2fa8@quicinc.com> Date: Wed, 29 Nov 2023 21:16:17 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH V2 3/5] arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts Content-Language: en-US To: Konrad Dybcio , , , , , CC: , , , , , , , , , , , , , , , , , References: <20231117113931.26660-1-quic_sibis@quicinc.com> <20231117113931.26660-4-quic_sibis@quicinc.com> <918ff1f5-ce01-43ea-b034-e69fbb31f495@linaro.org> <3dd41426-c026-a832-0a6b-0aabfaec2a8c@quicinc.com> From: Sibi Sankar In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: kGbA_WCg7lEFRzzOyBeObLXQRZK1LAKD X-Proofpoint-ORIG-GUID: kGbA_WCg7lEFRzzOyBeObLXQRZK1LAKD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-29_13,2023-11-29_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 priorityscore=1501 adultscore=0 impostorscore=0 bulkscore=0 mlxlogscore=999 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311290118 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/29/23 18:24, Konrad Dybcio wrote: > On 29.11.2023 10:25, Sibi Sankar wrote: >> >> >> On 11/18/23 06:36, Konrad Dybcio wrote: >>> On 17.11.2023 12:39, Sibi Sankar wrote: >>>> From: Rajendra Nayak >>>> >>>> Add base dtsi and QCP board (Qualcomm Compute Platform) dts file for >>>> X1E80100 SoC, describing the CPUs, GCC and RPMHCC clock controllers, >>>> geni UART, interrupt controller, TLMM, reserved memory, interconnects, >>>> SMMU and LLCC nodes. >>>> >>>> Co-developed-by: Abel Vesa >>>> Signed-off-by: Abel Vesa >>>> Signed-off-by: Rajendra Nayak >>>> Co-developed-by: Sibi Sankar >>>> Signed-off-by: Sibi Sankar >>>> --- > [...] > > >>>> +        idle-states { >>>> +            entry-method = "psci"; >>>> + >>>> +            CLUSTER_C4: cpu-sleep-0 { >>>> +                compatible = "arm,idle-state"; >>>> +                idle-state-name = "ret"; >>>> +                arm,psci-suspend-param = <0x00000004>; >>> These suspend parameters look funky.. is this just a PSCI sleep >>> implementation that strays far away from Arm's suggested guidelines? >> >> not really! it's just that 30th bit is set according to spec i.e >> it's marked as a retention state. > So, is there no state where the cores actually power down? Or is it > not described yet? > > FWIW by "power down" I mean it in the sense that Arm DEN0022D does, > so "In this state the core is powered off. Software on the device > needs to save all core state, so that it can be preserved over > the powerdown." I was told we mark it explicitly as retention because hw is expected to handle powerdown and we don't want sw to also do the same. > >> >>> >>> [...] >>> >>> >>>> +        CPU_PD11: power-domain-cpu11 { >>>> +            #power-domain-cells = <0>; >>>> +            power-domains = <&CLUSTER_PD>; >>>> +        }; >>>> + >>>> +        CLUSTER_PD: power-domain-cpu-cluster { >>>> +            #power-domain-cells = <0>; >>>> +            domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>; >>>> +        }; >>> So, can the 3 clusters not shut down their L2 and PLLs (if separate?) >>> on their own? >> >> on CL5 the clusters are expected to shutdown their l2 and PLL on their >> own. > Then I think this won't happen with this description > > every cpu has a genpd tree like this: > > cpu_n > |_CPU_PDn > |_CLUSTER_PD > > and CLUSTER_PD has two idle states: CLUSTER_CL4 and CLUSTER_CL5 > > which IIUC means that neither cluster idle state will be reached > unless all children of CLUSTER_PD (so, all CPUs) go down that low > > This is "fine" on e.g. sc8280 where both CPU clusters are part of > the same Arm DynamIQ cluster (which is considered one cluster as > far as MPIDR_EL1 goes) (though perhaps that's misleading and with > the qcom plumbing they perhaps could actually be collapsed separately) We did verify that the sleep stats increase independently for each cluster, so it's behavior is unlike what you explained above. I'll re-spin this series again in the meantime and you can take another stab at it there. -Sibi > > Konrad