From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 050B8C433EF for ; Tue, 9 Nov 2021 09:50:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E4625611CC for ; Tue, 9 Nov 2021 09:50:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245078AbhKIJwx (ORCPT ); Tue, 9 Nov 2021 04:52:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49200 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244163AbhKIJv0 (ORCPT ); Tue, 9 Nov 2021 04:51:26 -0500 Received: from mail-pf1-x430.google.com (mail-pf1-x430.google.com [IPv6:2607:f8b0:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F783C061767 for ; Tue, 9 Nov 2021 01:48:37 -0800 (PST) Received: by mail-pf1-x430.google.com with SMTP id y5so8695746pfb.4 for ; Tue, 09 Nov 2021 01:48:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=YpcZY/wok6Tm8gHdnpmkHhJcSgAyfMAyEx/8/I9XcUs=; b=mGhRu8rXvlsNA84eTFxwgWp9m4J1cKKFXXcfXNnU5SmA/pkHRGMEssXgsKzvqdOtDg AbmPPvpX0T1PWeOiulcDJTxnUxIycv4eP2lhi01SNVnXAI2kB4m4BgLpaq35HAoBSSvr IMcuDW9b4x6lGAFDFeH2vjsIYtCWj6aNEJibfUqHPgy7TAN9hOSHqlSs2r4dykj9Sc+b KTb9KXVFQ504U8s8dblYaCtb/EFmNJB6BPTjcgUcseDJdek1FI6cBiJcm4y+jGS4sMjA TlGXsEBao0qtmSocXSo1i25CEJR33YWZG15572i6x6Vs9yhEolrtXvQXMMaXF02kr+9j X2+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YpcZY/wok6Tm8gHdnpmkHhJcSgAyfMAyEx/8/I9XcUs=; b=ztgbfCBbKZG1EJ0lWGRbdnPkedejlS+5N0oYuX6R9aJatZudhlz/bfP1ikvUqxmYzq Hm6EI45vSqoZPWtugOIW5L0jxT7eajyZ8+Xah+blABVkCJDUA6Rmf1FWQqjUij52DiIc 79G2taQic6IWtdmnYKwoigTlMgxxSq57PuZ8nmLrt/VusoBeBgIMMFv/vja0uQHyHXQ+ FFq8UfM0U+zlvxgglsAjWMJkvoKrx4iyKlG+N2EvSxug7jbSAz/BScswkRFGvWHJ0Ww5 2+UsNfhI2GClBK6km75+qXpTEXrSAVDDDjwD4AlYADLvl8vaV8b4K1CamSgkoRJ406ps 408A== X-Gm-Message-State: AOAM5314P2ZX8Hya/+Hw9TCsbjcTZzRRQQU+qugQF37T6hjdiann9FcP X7JzkvIiSMMuMP7wdQXz1hxdara/awz0dw== X-Google-Smtp-Source: ABdhPJwYxHhoWKevx7Kz7vglYN8Vtc3KJug8o9ZQuEPuayY7jpZfqrWb3yV1tSEa/HNgEOaF2BR/7A== X-Received: by 2002:a05:6a00:2405:b0:44c:1ec3:8dbe with SMTP id z5-20020a056a00240500b0044c1ec38dbemr6680157pfh.33.1636451317028; Tue, 09 Nov 2021 01:48:37 -0800 (PST) Received: from hsinchu16.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id cv1sm1940511pjb.48.2021.11.09.01.48.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Nov 2021 01:48:36 -0800 (PST) From: Greentime Hu To: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu Subject: [PATCH v9 03/17] riscv: Extending cpufeature.c to detect V-extension Date: Tue, 9 Nov 2021 17:48:15 +0800 Message-Id: <802edef897b4bd40f3ebc2cb47c02b8e2f61a666.1636362169.git.greentime.hu@sifive.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Guo Ren Current cpufeature.c doesn't support detecting V-extension, because "rv64" also contain a 'v' letter and we need to skip it. Signed-off-by: Guo Ren Signed-off-by: Guo Ren Reviewed-by: Anup Patel Reviewed-by: Greentime Hu Signed-off-by: Greentime Hu --- arch/riscv/include/uapi/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/uapi/asm/hwcap.h b/arch/riscv/include/uapi/asm/hwcap.h index 46dc3f5ee99f..c52bb7bbbabe 100644 --- a/arch/riscv/include/uapi/asm/hwcap.h +++ b/arch/riscv/include/uapi/asm/hwcap.h @@ -21,5 +21,6 @@ #define COMPAT_HWCAP_ISA_F (1 << ('F' - 'A')) #define COMPAT_HWCAP_ISA_D (1 << ('D' - 'A')) #define COMPAT_HWCAP_ISA_C (1 << ('C' - 'A')) +#define COMPAT_HWCAP_ISA_V (1 << ('V' - 'A')) #endif /* _UAPI_ASM_RISCV_HWCAP_H */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index d959d207a40d..7069e55335d0 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -73,6 +73,7 @@ void __init riscv_fill_hwcap(void) isa2hwcap['f'] = isa2hwcap['F'] = COMPAT_HWCAP_ISA_F; isa2hwcap['d'] = isa2hwcap['D'] = COMPAT_HWCAP_ISA_D; isa2hwcap['c'] = isa2hwcap['C'] = COMPAT_HWCAP_ISA_C; + isa2hwcap['v'] = isa2hwcap['V'] = COMPAT_HWCAP_ISA_V; elf_hwcap = 0; -- 2.31.1