From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751684AbdKYRU2 (ORCPT ); Sat, 25 Nov 2017 12:20:28 -0500 Received: from mail-pg0-f67.google.com ([74.125.83.67]:35441 "EHLO mail-pg0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751277AbdKYRU1 (ORCPT ); Sat, 25 Nov 2017 12:20:27 -0500 X-Google-Smtp-Source: AGs4zManj/vc+DSPibnF0xfFOLcq2vcgBwEcQGZ7lekVdKoCj2M+yadN40BJEh6eztFULKfBkSox9Q== Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (Mac OS X Mail 10.3 \(3273\)) Subject: Re: [PATCH v2 2/2] x86: disable IRQs before changing CR4 From: Nadav Amit In-Reply-To: Date: Sat, 25 Nov 2017 09:20:23 -0800 Cc: LKML , linux-edac@vger.kernel.org, Andy Lutomirski , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Tony Luck , Borislav Petkov , Paolo Bonzini , =?utf-8?B?UmFkaW0gS3LEjW3DocWZ?= Message-Id: <803D7D69-1F01-4CB8-A966-A040F302D1C0@gmail.com> References: <20171125032907.2241-1-namit@vmware.com> <20171125032907.2241-3-namit@vmware.com> To: Thomas Gleixner X-Mailer: Apple Mail (2.3273) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by nfs id vAPHKY7a032090 Thomas Gleixner wrote: > On Fri, 24 Nov 2017, Nadav Amit wrote: >> /* Set in this cpu's CR4. */ >> -static inline void cr4_set_bits(unsigned long mask) >> +static inline void cr4_set_bits_irqs_off(unsigned long mask) > > This change is kinda weird. I'd expect that there is a corresponding > function cr4_set_bits() which takes care of disabling interrupts. But there > is not. All it does is creating a lot of pointless churn. > >> static __always_inline void setup_smep(struct cpuinfo_x86 *c) >> static __init int setup_disable_smap(char *arg) >> static __always_inline void setup_pku(struct cpuinfo_x86 *c) > > Why are you not doing this at the call site around all calls which fiddle > with cr4, i.e. in identify_cpu() ? > > identify_cpu() is called from two places: > > identify_boot_cpu() and identify_secondary_cpu() > > identify_secondary_cpu is called with interrupts disabled anyway and there > is no reason why we can't enforce interrupts being disabled around > identify_cpu() completely. > > But if we actually do the right thing, i.e. having cr4_set_bit() and > cr4_set_bit_irqsoff() all of this churn goes away magically. > > Then the only place which needs to be changed is the context switch because > here interrupts are already disabled and we really care about performance. > >> @@ -293,7 +303,7 @@ void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, >> } >> >> if ((tifp ^ tifn) & _TIF_NOTSC) >> - cr4_toggle_bits(X86_CR4_TSD); >> + cr4_toggle_bits_irqs_off(X86_CR4_TSD); You make a good point. I will add cr4_set_bit(). I will leave identify_cpu() as is, since it is rather hard to maintain code that enables/disables irqs at one point and rely on these operations at a completely different place. As you said, it is less of an issue once cr4_set_bit() and friends are introduced. Thanks, Nadav