Re: [PATCH 2/2] clk: divider: improve the execution efficiency of determine_rate()

[Chuan Liu <chuan.liu@amlogic.com>]

Hi Stephen,

Thanks for your review.

On 10/26/2025 9:25 AM, Stephen Boyd wrote:
> [ EXTERNAL EMAIL ]
> 
> Quoting Chuan Liu via B4 Relay (2025-10-21 03:12:31)
>> From: Chuan Liu <chuan.liu@amlogic.com>
>>
>> There is no need to evaluate further divider values once _is_best_div()
>> finds one that matches the target rate.
>>
>> Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
>> ---
>>   drivers/clk/clk-divider.c | 3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
>> index 2601b6155afb..b92c4f800fa9 100644
>> --- a/drivers/clk/clk-divider.c
>> +++ b/drivers/clk/clk-divider.c
>> @@ -339,6 +339,9 @@ static int clk_divider_bestdiv(struct clk_hw *hw, struct clk_hw *parent,
>>                          best = now;
>>                          *best_parent_rate = parent_rate;
>>                  }
>> +
>> +               if (best == rate)
>> +                       break;
> 
> This needs a comment. I'm not even sure if it is correct either, because
> the other exit from this loop happens if the parent rate can be

You're right.  Sorry, I was mainly focusing on the number of
iterations in the for loop earlier and missed the fact that the
parent clock directly participates in the division without changing.

> unchanged. I don't think we have any KUnit tests for this file, so
> please add some tests that deal with this case explicitly (the parent
> rate being unchanged as the desirable part).

I'll take some time to get familiar with the principles and methods
of KUnit testing, and I'd be happy to help improve it.

> 
> A general comment: these patches have no benefit described in the commit
> text. Do you see any performance improvement with this patch? I sorta
> doubt this really matters because the number of dividers are typically
> small. A single sentence commit text that only says there is no need
> doesn't convince me that any work has been put in to research why the
> code was written this way or even prove that making this change improves
> anything.

This patch came about because I noticed that the mux has a similar
logic:
- Even after finding a suitable clock source, it continues to iterate
through and calculate other sources (and even if a later source has
the same rate, it won't replace the current one).

 From there, I went on to examine the divider logic, but I missed the
detail that the parent clock doesn't change in the divider. Sorry
that this unreasonable patch ended up taking up your time.