From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=100.103.45.18 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1793791768; b=gIIYPhlHRkHKk1l3bbByZ/BW7xDomjasdK/UAM+FCw5ERE78SJITXynGZ8BlP6zfTROf XvSRpJuC+u+/FmFQAe+8+KIGAnvfsKZQWUFDCAtLHULelGSR2XDZGY9ZD5Xw40QZsx1jI YESABY4Fzl14eB5/KpGkCZeHs4WN/+I+0P4QOr4fDAJ83FqTKHDJ+PZGgRtVy4lF4tLxR rCClsd0spzDNX12CdvOyaJPYorUu4OKFpyuVy/m/1wbo1dJLB8DP4LdC5ouYwVbAT0LYE 9aWvD/UboAX/60OJ3VAny/fOJHhExuCAcauxx/UKgpm5vxalI4bK6ACsO24mwWBK5dA== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1793791768; h=Received:DKIM-Signature:Message-ID:Date:MIME-Version:User-Agent: Subject:To:Cc:References:From:Content-Language:Autocrypt:In-Reply-To: Content-Type:Content-Transfer-Encoding; bh=Btdf0uqMiUKY16BRcSVyrMGCAxEDA4RyrShdMRLVVN0=; b=XCrWrrY48yJff+rS+8t1i5UeppZCZQ21Ilu9KBrKB4jftZChpqc7JQo4nSz9dooSE0iy 15yhJyHgaV0MlZ8VoH+tTk+pN+t5dOxa3J1nZ+KW+fcBe44ftHBv66XHYK68lKUlQa3lv yJWFHy4iIAcjYI3lCbIi/AB6otpx8GFOE1pM50c5/3I6pGKkEvrsnKRqK6gS/UUHCZADR qa1a+nRjePUlMebXRn9YBZYRQZSyuLstn+nrfOL3k0OT7+sGyEzqsnNnm+z6/r5X8c7Tu HGjec1kxH9O/0juTLkXc6vPUuJIc1p07nygFcNQznJgpfxMoZiX45w0Gbl4GDdpLIfQ== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=dZ5Sy4BS; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7FBE0606A32F; Wed, 4 Nov 2026 11:29:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=dZ5Sy4BS Received: by smtp.kernel.org (Postfix) with ESMTPSA id 951931F00A16; Wed, 4 Nov 2026 11:29:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1793791768; bh=Btdf0uqMiUKY16BRcSVyrMGCAxEDA4RyrShdMRLVVN0=; h=Date:Subject:To:Cc:References:From:In-Reply-To; b=dZ5Sy4BSYu7R9+UVp1mhpTolnmh4Q/e+aziPeaIKS2CBRIvQCrz8OkzFENwVenppn OeqXwHjEUHoZATk3hN32IfeAdfiNqQlGz/M9gJ6ogOJJ/jJacTiCh+Mgky37BCpF7U DfBNkvqtJshG/s0wE2uv9W0LZTQwXaqz2q5DOzlfaBJWUIm8anSG+kwPoVwFKvdyDN TF+upsvAoNE38tch5WTFZQDAjplf+pkWzqLmx+N5HWmuvEyKWpzkr8+FvLINGti51F FcGyqmAhXgQAkGU9CekWFvMVovs9Xfba/OjX2eD7vGbAG2r6eayK4edCTfZcWsidUC GcbTj394uABuQ== Message-ID: <803d16ba-49c9-404c-8973-e4d4dc02b1e3@kernel.org> Date: Wed, 4 Nov 2026 11:29:23 +0000 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/5] dt-bindings: phy: qcom: Add common qcom,csi2-phy To: Anusha Arun Nandi Cc: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , gjorgji.rosikopulos@oss.qualcomm.com, hariram.purushothaman@oss.qualcomm.com, akapatra@quicinc.com, jigarkumar.zala@oss.qualcomm.com, linux-phy@lists.infradead.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20261103214105.3605181-1-anusha.nandi@oss.qualcomm.com> <20261103214105.3605181-2-anusha.nandi@oss.qualcomm.com> From: Bryan O'Donoghue Content-Language: en-GB Autocrypt: addr=bod@kernel.org; keydata= xsFNBGRJNSgBEADD7Vm2ZFa+v+JGJ2QYTJqQAkqis/uOHkhdFNXqpBarVBd47QU/DMNU5Rxg jedMQEmHoeDbJ6UOpjbrUQ63c5sgG1JbroHJJctwsEI75OOlekMuebEbjIJBLfgENGwPBMHv piv5TgCWr0VgYaXfp2eh2LINFywzqj823HiDPibQAXDrjzvF1ogksi/6cQZs8d4if8YQkLOr YISFouG+eR0nN1I7mUfIddXOWu6lJeTyqbWVurv58k2ekIXKaOC9ixLHFbcfYV0hOgRaTwQC B8CYF9nfqZla19iItfsN9QxN+ZdQjcRoYipp6HPCMfJlKH7GfaFcW93LKc4DKJ2lVL+pg/OQ lythZbjRPY492NG9kZ65aYstCs90uhMUEVVPuGUw7wBEku+6IEwZfrbMVKeWzLlPyM4Hv9hM 8ktxSmxWsPTPqpBC8eyeAQLalMELAyVcZlkaCtEcbj7w4l/JkYz+4l37obG8ZD+B34udBUUz MsAJ8foDFrBh2MOFA3hxD6G90D23mmWsri7pnKA2tZs92aQX7Ee+FbCyg6g5ln62Sq83ZDbf 53DdBs55EVpBadeInWmXhzCHPQx06H+CwTEjShTYIaMmBfrewvYUDKvFTC5iKQhAEUgt6i94 JsbG7NoeqcxkUMcBOEUQ3uCQG1D70ugspgXc0wd3Rimiq6535wARAQABzSFCcnlhbiBPJ0Rv bm9naHVlIDxib2RAa2VybmVsLm9yZz7CwZEEEwEIADsWIQTmk/sqq6Nt4Rerb7QicTuzoY3I OgUCZ+R+mwIbAwULCQgHAgIiAgYVCgkICwIEFgIDAQIeBwIXgAAKCRAicTuzoY3IOimUD/94 BwVEJX31JRe2sxbB/e1w2p8x1bxvTw5AeIzpV3ox7coJg1bSU2mnGuj1V4o0Yxf/3zmcJzCN VfVjwRF8Ii3GnC7uUXk2t+87piQfKTyJAYQABhZUKgoVJbjJq/S+C3XCKIyBA+EiezoUsgsA jTzwU+FzV7zVWIXFPJNtBERLwboE9w9U3KjAExOa1kSY8eLrsg6kOwlOHWy5UsQqYOjrS96M mzm2xuc1+RCjrndAyYhCnrOKvJ67HsPnBeJCjw7ImGD/U1GchwYbX8o3DO3JNHm3qfC86ZqX 2sCouENg4OzgPTtLKUrueM6xsu6KMM7gj17vxsiR3KQEoJnnMB8D1xtBofN3mFZE0wD9M24m 8yGunZbtntMCUHzIrlJgAPwKWKuGOYtA8UgMTFkccnUJtQrg9KotKtEF/FuftG9zLG9XEkt4 5ZdNgbSoLWgelu3T47mbOJ8LHhiLaCWP7yrovtVAvLUQ1BsiA42u8ECrFCFvQj9nrejE/ICv kP+uqcKtdDvP9HrIGycF1WZyfZLp0RvopKW92FLvI4I1QFWJ+wenk6+LGyJ5bzlrWzevjxmf nHcXE6sJBHrE7eijlbbImDAi3uLYN8Nd9Dm11IDAy4GAIQxSiQn0yblDhPiyGtchy80EVkCm g9k17Wol+2E2mC4DKgVdCkyUtTRSLgsJCs7BTQRkSTUoARAAuTnmWHBS6izRcEE93ajpzI7h dgQO4U3IRvOEsvIKR5NGcNEs0ngGebwsZ/lVULjN4vYU0LleqVhPBidNXUoZCN3A0F0Z2Ov8 NZdef+2EhQPBVWxFO7JBzhe8Z3ALj+wFtlg8akJjBzU56azW/iJzAobqHVrudzKoO2b1/CMg VbiAQ+RXjgfN5kY/HqYDU7mw+hXuUV9PbtX1L8xqQQac95oM9rHzKHHpiVwxTeJnGQsa+THi Kze+YET3rCoGHMvOQEJhdrucTv5FpAakKdkOFNel9FFckLRKEuWgCzhpFsjQ7xbirQgFUxG9 vlk1+q4hMRGNyEqoD6svYEeqbiUSd0oPUJeioiC3rNMRCNHLVrfZ2J6SCPkxfda08uzSdDQU 1/YPjOh8ZtQDMu7WctZ3XO288Z1gyBR49V7fbFs2w4sQxG+h/enlxqP7fdw1mjUlZjU5huCJ ielS0oEaIpmUpkugli7x4WhwLnhK2EbSoz7nLBC0y+ALUOdMlz/Y1l9xRt+bkDhpmf4O4IcI MxgZ0QMLq8rHDkGaEbsgZZHQPS58T0XE3IP30Q9SNxsruCMXtd2hYtBssf/wohc6JVsTtMg2 VYTPDPIFNZFSXupEJB7jlqpDWJ8ooJfJRLBatbjT5+mVQaMYB7Hs/t+zWYWaJKHyc8O6WLEC NUV5Tdt5EkkAEQEAAcLBdgQYAQoAIBYhBOaT+yqro23hF6tvtCJxO7Ohjcg6BQJkSTUoAhsM AAoJECJxO7Ohjcg6LuIQALnXt36OUuK43wqw6UYt0cnN6EbUqJHApAF5eNFn0jCCB2XELjSz JKJwuNAweowBdabiBniJ+501WIW+ewEsz1uby5fUQjZuCEsIkuaIluyfUFPb73qrQyAGuusd 7teA4WT+/jUku9g7lX5sVoRCrKQPkd16f6Bzfztyqyjcn43/X5yQI+wlboQ6HuKe/3I3yiOx OgmCHzOawpC9PvhEcKj79RLM3Zz5Ts5AuHpRX70Jz8Be76LwVFLp5Msx3S24ZTU1lBo2uiJ3 xSkay2lTpyVWRPx9vgcwzxGguOPJQJwsQeLb7wpoJMPpD3ERoaRii7Q7hvmxklpZjhKYWB3d t6nQ497Ek9loCrp3MIjRCSDN5xEGffiHks9yTeGMUQwO4tX8RE04uOJPkUY7uCFzFqN6/qey X3oFfPgkULMdiHofPAL1OskZSTzGPSfTYRE46NCJw8yoZBQ/oOyWeqaUQbK0wmW/g81wm8p7 LKSGEglMpiX07M1AotgvylN5C8fjbouoK+/RAMsXkk8jba6rPfuuXPaDjCyyKn6zSVHETnHW 3AJbgVY50T8STpnxayBQvWbCvu+6NOEjXCbyaOJig+5l0zlGN9XHjdANXC5HnwmyaGRL9YDq Jh2nVXVJDincOdQRdKcJjYLqaOAoWrYWSDi1iZGspHBTDrnOvfMQzzHY In-Reply-To: <20261103214105.3605181-2-anusha.nandi@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 03/11/2026 21:41, Anusha Arun Nandi wrote: > SA8775P, QCS8300 and SC7280 CSI2 PHYs are bit-for-bit identical in > devicetree shape (ports, bus-type, data-lanes, operating-points-v2, > clocks, single "top" power-domain, vdda-phy/vdda-pll supplies). > > Describe all three with a single qcom,csi2-phy.yaml and a compatible > oneOf, rather than one standalone schema per SoC. QCS8300 is further > required to be paired with a qcom,sa8775p-csi2-phy fallback > compatible, the same way other Qualcomm bindings express full > hardware compatibility between two SoCs (see qcom,qusb2-phy.yaml); > this lets the driver bind QCS8300 nodes via its qcom,sa8775p-csi2-phy > match entry rather than carrying a duplicate one. > > qcom,x1e80100-csi2-phy.yaml is a separate PHY with a different shape > (3 clocks, 3 power-domains, different supply names, DPHY split-mode > support) and is left untouched. > > Reviewed-by: Jigarkumar Zala > Signed-off-by: Anusha Arun Nandi > --- > .../bindings/phy/qcom,csi2-phy.yaml | 176 ++++++++++++++++++ > 1 file changed, 176 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/qcom,csi2-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/qcom,csi2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,csi2-phy.yaml > new file mode 100644 > index 000000000000..5d25547528bd > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/qcom,csi2-phy.yaml > @@ -0,0 +1,176 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +# Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/qcom,csi2-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm CSI2 PHY > + > +maintainers: > + - Anusha Arun Nandi > + > +description: > + Qualcomm MIPI CSI2 D-PHY. Connects MIPI CSI2 sensors to Qualcomm's Camera > + CSI Decoder. > + > +properties: > + compatible: > + oneOf: > + - enum: > + - qcom,sa8775p-csi2-phy > + - qcom,sc7280-csi2-phy > + - items: > + - enum: > + - qcom,qcs8300-csi2-phy > + - const: qcom,sa8775p-csi2-phy > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 2 > + > + clock-names: > + items: > + - const: core > + - const: timer > + > + interrupts: > + maxItems: 1 > + > + operating-points-v2: true > + > + opp-table: > + type: object > + > + power-domains: > + items: > + - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller. > + > + power-domain-names: > + items: > + - const: top > + > + vdda-phy-supply: > + description: Phandle to PHY supply. > + > + vdda-pll-supply: > + description: Phandle to PLL supply. Why are we departing from vdda-0p9-supply and vdda-1p2-supply ? Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/$defs/port-base > + description: > + Sensor input. A single sensor is described by a single endpoint > + with one to four data lanes, numbered 1-4. The clock lane is > + position 0. Since you've cloned and owned the yaml - you've also dropped the description of DPHY split mode. > + > + unevaluatedProperties: false > + > + properties: > + endpoint: > + $ref: /schemas/media/video-interfaces.yaml# > + unevaluatedProperties: false > + properties: > + bus-type: > + enum: > + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY > + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY > + default: 4 > + > + data-lanes: > + minItems: 1 > + maxItems: 4 > + items: > + minimum: 1 > + maximum: 4 > + description: > + Data lane positions following this endpoint's clock > + lane. Positions are a per-port logical numbering, not > + package pad or ball positions. > + > + required: > + - data-lanes > + - remote-endpoint And then you've dropped the DPHY split mode defintion NAK Please either clone and own the whole DPHY split-mode circus or just modify the existing definition to include your new stuff. > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: Output to the CAMSS CSID controller. > + > + required: > + - port@0 > + - port@1 > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - interrupts > + - operating-points-v2 > + - power-domains > + - power-domain-names > + - vdda-phy-supply > + - vdda-pll-supply > + - ports > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + > + phy@ac9c000 { > + compatible = "qcom,sa8775p-csi2-phy"; > + reg = <0x0ac9c000 0x2000>; > + > + clocks = <&camcc CAM_CC_CSIPHY0_CLK>, > + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; > + clock-names = "core", > + "timer"; > + > + interrupts = ; > + > + operating-points-v2 = <&csiphy_opp_table>; > + > + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; > + power-domain-names = "top"; > + > + vdda-phy-supply = <&vreg_l4a>; > + vdda-pll-supply = <&vreg_l1c>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + csiphy0_in: endpoint { > + bus-type = ; > + data-lanes = <1 2 3 4>; > + remote-endpoint = <&sensor_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + csiphy0_out: endpoint { > + remote-endpoint = <&csid_in>; > + }; > + }; > + }; > + > + csiphy_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + }; > + }; > + }; > -- > 2.34.1