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Miller" , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , "Russell King (Oracle)" , Nazim Amirul , netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH net] net: stmmac: dwmac-motorcomm: mask the MISC interrupt In-Reply-To: <20261102080938.2955-1-magnusleatti@kernelriot.com> References: <20261102080938.2955-1-magnusleatti@kernelriot.com> Message-ID: <805aeb73d9e32b237bcb30c8fd44ffed@tipi-net.de> X-Sender: nb@tipi-net.de Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit X-Last-TLS-Session-Version: TLSv1.3 Hi Magnus On 2.11.2026 09:09, Magnus Leatti wrote: > [...] > Russell, d3265c19b35d ("net: stmmac: xgmac2: disable RBUE in default RX > interrupt mask") describes a similar storm on xgmac2. Should dwmac4 do > the same? I have only tested the glue change. AFAIU RBU is the cause. Dropping it in dwmac4, as Russel did in d3265c19b35d, would cover all multi-MSI users. > > drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c > b/drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c > index 124fcd55a..610d533b9 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c > @@ -30,6 +30,7 @@ > #define OOB_WOL_CTRL 0x1010 > #define OOB_WOL_CTRL_DIS BIT(0) > #define MGMT_INT_CTRL0 0x1100 > +#define MGMT_INT_CTRL0_MASK_MISC BIT(21) Where is this bit documented? The vendor driver? > #define INT_MODERATION 0x1108 > #define INT_MODERATION_RX GENMASK(11, 0) > #define INT_MODERATION_TX GENMASK(27, 16) > @@ -172,7 +173,11 @@ static void motorcomm_reset(struct > dwmac_motorcomm_priv *priv) > > static void motorcomm_init(struct dwmac_motorcomm_priv *priv) > { > - writel(0x0, priv->base + MGMT_INT_CTRL0); > + /* > + * Nothing services the MISC source, and once raised it never > + * deasserts, so keep it masked. > + */ > + writel(MGMT_INT_CTRL0_MASK_MISC, priv->base + MGMT_INT_CTRL0); Doesn't this turn off the stmmac MAC irq on vector 5 completely? If so, please mention it in the comment. Also, does the MSI fallback still get RX/TX interrupts with MISC masked? > [...] Thanks, Nicolai