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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-330607b1fccsm12530565a91.14.2025.09.22.02.19.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 22 Sep 2025 02:19:46 -0700 (PDT) Message-ID: <808e57a4-8f1e-4870-894e-2eb05ec7a134@oss.qualcomm.com> Date: Mon, 22 Sep 2025 17:19:40 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC 1/3] coresight: tmc: add the handle of the event to the path To: Leo Yan Cc: Carl Worth , Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Tingwei Zhang , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20250922-fix_helper_data-v1-0-905e8115a24e@oss.qualcomm.com> <20250922-fix_helper_data-v1-1-905e8115a24e@oss.qualcomm.com> <20250922082920.GB516577@e132581.arm.com> Content-Language: en-US From: Jie Gan In-Reply-To: <20250922082920.GB516577@e132581.arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: R-yNXmONtwdrKVs096jrtLoIOPyEDLFQ X-Authority-Analysis: v=2.4 cv=RO2zH5i+ c=1 sm=1 tr=0 ts=68d114b5 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=ck2vDrGU2QCsmqff:21 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=vzhER2c_AAAA:8 a=EUspDBNiAAAA:8 a=7CQSdrXTAAAA:8 a=ZO4bw9XDxdbX_LlL1T4A:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 a=0YTRHmU2iG2pZC6F1fw2:22 a=a-qgeE7W1pNrGK8U0ZQC:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTIwMDAyNSBTYWx0ZWRfX8oOVJy7o7gST fkDqQ2DFTZc0/dxw7++AemKQbozBUZuT02dxG7PrYXJlIpMEhl71LiEsbAOjgpOrYriXKw2tSz+ WTBQQmjWQa/+PoBwWUjG0PBUjFRW0K/91o2wEGeOHhwhCh5PLWoFtvoQINXoXipshAU13RrG1xp q7BBXe6/tTvfd6QxzD8quSMkS1o8uXdY8+GlYvQ3dZeht6mg5bQWAC60BY3aGygIMan/XtY+d+9 67rkJdSEtNaCuxrdLgguLRtJDB/Qus681RGWRLS4YRAzNRsAIGnZTQl+NfSPHFh+ZddLMwqwN0X oTXYEOKccG9DOXhdQCt8JVNVl1Zr7ydYGUsn1TA32EnSU65DOMTEp/t8ogrynx1tR7d6RPgVKcx gOtG9SsX X-Proofpoint-ORIG-GUID: R-yNXmONtwdrKVs096jrtLoIOPyEDLFQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-22_01,2025-09-19_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 suspectscore=0 priorityscore=1501 impostorscore=0 spamscore=0 adultscore=0 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509200025 On 9/22/2025 4:29 PM, Leo Yan wrote: > On Mon, Sep 22, 2025 at 03:31:39PM +0800, Jie Gan wrote: >> From: Carl Worth >> >> The handle is essential for retrieving the AUX_EVENT of each CPU and is >> required in perf mode. It has been added to the coresight_path so that >> dependent devices can access it from the path when needed. >> >> Fixes: 080ee83cc361 ("Coresight: Change functions to accept the coresight_path") >> Signed-off-by: Carl Worth >> Co-developed-by: Jie Gan >> Signed-off-by: Jie Gan >> --- >> drivers/hwtracing/coresight/coresight-etm-perf.c | 1 + >> drivers/hwtracing/coresight/coresight-tmc-etr.c | 3 ++- >> include/linux/coresight.h | 10 ++++++---- >> 3 files changed, 9 insertions(+), 5 deletions(-) >> >> diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c >> index f677c08233ba..5c256af6e54a 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm-perf.c >> +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c >> @@ -520,6 +520,7 @@ static void etm_event_start(struct perf_event *event, int flags) >> goto out; >> >> path = etm_event_cpu_path(event_data, cpu); >> + path->handle = handle; >> /* We need a sink, no need to continue without one */ >> sink = coresight_get_sink(path); >> if (WARN_ON_ONCE(!sink)) >> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c >> index b07fcdb3fe1a..1040f73f0537 100644 >> --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c >> +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c >> @@ -1327,7 +1327,8 @@ static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev) >> struct etr_buf *tmc_etr_get_buffer(struct coresight_device *csdev, >> enum cs_mode mode, void *data) >> { >> - struct perf_output_handle *handle = data; >> + struct coresight_path *path = data; >> + struct perf_output_handle *handle = path->handle; >> struct etr_perf_buffer *etr_perf; >> >> switch (mode) { >> diff --git a/include/linux/coresight.h b/include/linux/coresight.h >> index 6de59ce8ef8c..4591121ae1d4 100644 >> --- a/include/linux/coresight.h >> +++ b/include/linux/coresight.h >> @@ -332,12 +332,14 @@ static struct coresight_dev_list (var) = { \ >> >> /** >> * struct coresight_path - data needed by enable/disable path >> - * @path_list: path from source to sink. >> - * @trace_id: trace_id of the whole path. >> + * @path_list: path from source to sink. >> + * @trace_id: trace_id of the whole path. >> + * struct perf_output_handle: handle of the aux_event. > > s/struct perf_output_handle/@handle/ Hi Leo, Thanks for pointing out. I actually missed this error during the code review... Jie > > Otherwise, LGTM: > > Reviewed-by: Leo Yan > >> */ >> struct coresight_path { >> - struct list_head path_list; >> - u8 trace_id; >> + struct list_head path_list; >> + u8 trace_id; >> + struct perf_output_handle *handle; >> }; >> >> enum cs_mode { >> >> -- >> 2.34.1 >> >>