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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b9d6e5c5824sm403077566b.38.2026.04.14.07.09.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 14 Apr 2026 07:09:58 -0700 (PDT) Message-ID: <809e2ad6-258c-49ac-9f3b-4ced32807203@oss.qualcomm.com> Date: Tue, 14 Apr 2026 16:09:55 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 05/11] media: iris: Enable Secure PAS support with IOMMU managed by Linux To: Vishnu Reddy , Bryan O'Donoghue , Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joerg Roedel , Will Deacon , Robin Murphy , Bjorn Andersson , Konrad Dybcio , Stefan Schmidt , Hans Verkuil Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, Mukesh Ojha References: <20260414-glymur-v1-0-7d3d1cf57b16@oss.qualcomm.com> <20260414-glymur-v1-5-7d3d1cf57b16@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260414-glymur-v1-5-7d3d1cf57b16@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: wljRK6Rb6VaPXsS5MELWIdjKZqamto5C X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDE0MDEzMyBTYWx0ZWRfX4eDhZGrOrtM1 RrusSVOV4c5RK1CxzsGJ8O3AuUNkSAeCB70IOqwPIynTsYZsRb9pA0U2lnDaDbaVzFVTJBm/tSR H64uxPaZbizeTlGNFe7iBXbKVlZWdBsWxmHk81TNOB+oIcOdMppg4ZXVItf0GcFYJiTTRZwLBcC aZIejGobn/EQ0+j2KFa0iVWw6ZyQ5UXl4Um5ploRkcVVvfjJTXvYmuU3s0kjpTWURfNVD8R2I77 +BDsjNkrUvUUpvNt1Qc5PHG9Rd1POY6Y+C/9N4Cw2pEauRfE79hka+HoBpIuzcwCOiz8a+esxbZ jIDTBibQJks9zZlL77j3MMCOdwzxmQsgwBmcO5Cjs7DVTh2wkggtmov/TWdscRMCbeFXUoGuBHU G2NC+p2BL2LNQJBGVePOA9K65ABA29juJFQ/lYrRr4nhtI7IDmDPFUHhaZ0XCDf3+akInF0QPvn MPQOIJpWm4gEQ/GMINw== X-Proofpoint-ORIG-GUID: wljRK6Rb6VaPXsS5MELWIdjKZqamto5C X-Authority-Analysis: v=2.4 cv=DrpmPm/+ c=1 sm=1 tr=0 ts=69de4ab9 cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=BowHXwPdtatiOUMbaTwA:9 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-14_03,2026-04-13_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 adultscore=0 spamscore=0 bulkscore=0 malwarescore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604140133 On 4/14/26 7:00 AM, Vishnu Reddy wrote: > From: Mukesh Ojha > > Most Qualcomm platforms feature a proprietary hypervisor (such as Gunyah > or QHEE), which typically handles IOMMU configuration. This includes > mapping memory regions and device memory resources for remote processors > by intercepting qcom_scm_pas_auth_and_reset() calls. These mappings are > later removed during teardown. Additionally, SHM bridge setup is required > to enable memory protection for both remoteproc metadata and its memory > regions. > > When the hypervisor is absent, the operating system must perform these > configurations instead. > > Support for handling IOMMU and SHM setup in the absence of a hypervisor > is now in place. Extend the Iris driver to enable this functionality on > platforms where IOMMU is managed by Linux (i.e., non-Gunyah, non-QHEE). > > Additionally, the Iris driver must map the firmware and its required > resources to the firmware SID, which is now specified via iommu-map in > the device tree. > > Co-developed-by: Vikash Garodia > Signed-off-by: Vikash Garodia > Signed-off-by: Mukesh Ojha > Signed-off-by: Vishnu Reddy > --- [...] > static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name) > { > + struct device *dev = core->dev_fw ? core->dev_fw : core->dev; Maybe: struct device *fw_dev = core->dev_fw ?: core->dev; and preserve *dev to be the main Iris device? Konrad