From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 20FE5256D for ; Wed, 19 Nov 2025 01:07:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763514432; cv=none; b=F4eQkWwZPytcwn6v2mOz3b9G4ZJUkJll6wi+eNzM0IMGyUonJxh+6h/pb9EwM6y0MgMx6vjYAqMIj1ZKDWJwv8v1CGux+v6u7THdf6NehKLZ2oyviWG8QR6rUtQDkxXur8WR6HQtrMM1xP4WrZv+txZcbB1FbG7JJR7ss/hfjto= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763514432; c=relaxed/simple; bh=jmea5zmU9TQ5M193PDxgNnSpz8XuIE3R6lacjabpJHU=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=oJckCkW+xIUHEz23P17htVg944Fw82PfRrn/m7GeUgDLoVyU8F9PteBB197ObXHJ25xnXWMoU3v95cbMCtzNIa84W1VSrGkACwwu1Y+89B1dlTqqh8H/jdkTHJmIRzl1ti+1FFXXXZ8F8tpsx4HkdH3/fr0eSrbl0YnNlttL6WA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6C1F72B; Tue, 18 Nov 2025 17:06:58 -0800 (PST) Received: from [10.163.45.240] (unknown [10.163.45.240]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BDBAD3F66E; Tue, 18 Nov 2025 17:07:03 -0800 (PST) Message-ID: <80c7af9b-ac6a-42fe-981f-c4b6f2cc9d7f@arm.com> Date: Wed, 19 Nov 2025 06:37:00 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/6] arm64/mm: TTBRx_EL1 related changes To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Ryan Roberts , Ard Biesheuvel , linux-kernel@vger.kernel.org References: <20251103052618.586763-1-anshuman.khandual@arm.com> Content-Language: en-US From: Anshuman Khandual In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 14/11/25 3:25 PM, Mark Rutland wrote: > On Thu, Nov 13, 2025 at 02:48:44PM +0530, Anshuman Khandual wrote: >> On 03/11/25 10:56 AM, Anshuman Khandual wrote: >>> This series contains some TTBRx_EL1 related changes, aimed at standardizing >>> TTBRx_EL1 register field accesses via tools sysreg format and also explains >>> 52 PA specific handling methods via a new macro along with in code comments >>> >>> This series applies on v6.18-rc4 >>> >>> Cc: Catalin Marinas >>> Cc: Will Deacon >>> Cc: Ryan Roberts >>> Cc: Ard Biesheuvel >>> Cc: linux-arm-kernel@lists.infradead.org >>> Cc: linux-kernel@vger.kernel.org >>> >>> Anshuman Khandual (6): >>> arm64/mm: Directly use TTBRx_EL1_ASID_MASK >>> arm64/mm: Directly use TTBRx_EL1_CnP >>> arm64/mm: Represent TTBR_BADDR_MASK_52 with TTBRx_EL1_BADDR_MASK >>> arm64/mm: Ensure correct 48 bit PA gets into TTBRx_EL1 >>> arm64/mm: Describe 52 PA folding into TTBRx_EL1 >>> arm64/mm: Describe TTBR1_BADDR_4852_OFFSET >>> >>> arch/arm64/include/asm/asm-uaccess.h | 2 +- >>> arch/arm64/include/asm/assembler.h | 3 ++- >>> arch/arm64/include/asm/mmu_context.h | 2 +- >>> arch/arm64/include/asm/pgtable-hwdef.h | 23 ++++++++++++++++++++--- >>> arch/arm64/include/asm/pgtable.h | 5 +++-- >>> arch/arm64/include/asm/uaccess.h | 6 +++--- >>> arch/arm64/kernel/entry.S | 2 +- >>> arch/arm64/kernel/mte.c | 4 ++-- >>> arch/arm64/mm/context.c | 8 ++++---- >>> arch/arm64/mm/mmu.c | 2 +- >>> 10 files changed, 38 insertions(+), 19 deletions(-) >> >> Gentle ping. Beside [PATCH 4/6] (which can be dropped as indicated by Mark) >> any concerns regarding reset of these changes here ? > > Overall I don;t think this series actually improves anything; it just > shuffles things around, and leaves conversions half-done. I don't think > we must take this as-is. > > For patches 1 and 2, the changes would be fine if we were also getting > rid of TTBR_ASID_MASK and TTBR_CNP_BIT, but we don't, apparently because > those are still used by KVM. It feels like those two patches should be > split into a separate series that *only* moves code over to generate > sysreg definitions, also updates KVM, and removes the unused legacy > definitions. Sure thing. I will spin out a separate series as suggested. > > For patch 3, I think the change makes the code harder to read, and > harder to understand, because there's no context to explain why we're > masking out a single bit. I don't think this is actually an improvement. We are masking out a single bit here as per the ARM DDI 0487 L.B in the page number D24-8540. ------------------------------------------------------------ When TTBR0_EL1.BADDR represents a 52-bit addresses, all of the following apply: • Bits A[51:48] of the stage 1 translation table base address bits are in register bits[5:2]. • Register bit[1] is RES0. • The smallest permitted value of x is 6. • When x>6, register bits[(x-1):6] are RES0. ------------------------------------------------------------ Is not deriving the applicable address mask in the 52 bit PA context from the original base address mask better than hard coded mask GENMASK_ULL(47, 2) ? Just wondering - would it be better to add some more context in the comment above it ? > See below for related notes for patch 5. > > For patch 4, as above, I think the patch can be dropped. Agreed. > > For patch 5, this could be OK, but we should define > TTBR_BADDR_52_PA_PIVOT as (51 - 5) and avoid the magic number entirely. Agreed. > IMO it'd be nicer to just extract and re-insert the bits; I think our > current logic is unnecessarily micro-optimized so that this can be > implemented with a shifted-OR + AND, whereas I think we could burn a > temporary register and use BFX + BFI + AND, and that would be clearer as > to *which* bits we're trying to move. Will that only be applicable for phys_to_ttbr()'s assembly variant and the macro definition in which does the right shifted OR followed by AND still remains unchanged ? > > For patch 6, I guess this is fine; I don't have a strong feeling either > way. IMHO it will be great to have this patch included.