From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DAC8113DB9F; Mon, 16 Sep 2024 09:03:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726477414; cv=none; b=AVKMRj9DAa0zVcx37PKcnDXpreaj9j3GBQI9LAaA29+vPLyyHEpn62BPImfhiCmcHqKSMyW6Zyv4BaaBSEQ2LjSfdCR21f94yY86PCWUIwzJLk9QGCzPo3zjVbIlQVN9fEB7nr088e2srJI2/3TPaLjmUa+gI3T4mIBgMkV1r2Q= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726477414; c=relaxed/simple; bh=o+oy6yz8phkO+UfYBB1PUM39dfktmBISvJLGaPaMgEA=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=W7pAzOlovpyvFiG1si3EgBb9JWGghVDh18BwdfrtLzsNipX82ctktmoo0lc3u2MJzRKY3fwNwGatcMEIH75iOgmtNlUxJepBk6kgTijqzHzI3wyrpmjJ/pxF2IPyKEZ/IDInGSzFAWqHE7VP7JxH/O/RbkbY6QN8CeHnNHtTsaQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=UkMrg9Do; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="UkMrg9Do" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 76041C4CEC4; Mon, 16 Sep 2024 09:03:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1726477413; bh=o+oy6yz8phkO+UfYBB1PUM39dfktmBISvJLGaPaMgEA=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=UkMrg9DocoTWd5N/Yy67FZDXoWQkQEYKOCAAmz+L3A+3N6Og6RL20vgurfdax8Vjr gBefU5ycvT3vQKywJlfKSNzmzUHfy7qyCwREet4l1L8lhE0sVx6IfNzQqfzifUIN4O KD4j5KhU3KDqephWhRMt4xxnHx6HzTOy/0F4p8bA91zE3mOYGxIxu8w87+6HYJsXvN +myJH+AELRJyK1d4IYEPu+XkZduMKY4kTvaLvCQ8cwRDNvN8YB6RU7G5GDORwuNonZ ysA8W5EjasxMyZ5c8513H9qJ9lVe9k4lBgWoHyvOhYnbFtf32pZ+yZPw/137q4w01Z 9tAxwX8Qy/zcg== Message-ID: <80ca3719-1c7f-4899-b533-faf3c9093444@kernel.org> Date: Mon, 16 Sep 2024 11:03:25 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/5] clk: qcom: lpassaudiocc-sc7280: Add support for LPASS resets for QCM6490 To: Dmitry Baryshkov Cc: Taniya Das , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , quic_imrashai@quicinc.com, quic_jkona@quicinc.com, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20240816-qcm6490-lpass-reset-v1-0-a11f33cad3c5@quicinc.com> <20240816-qcm6490-lpass-reset-v1-2-a11f33cad3c5@quicinc.com> <67819a53-8e99-469b-a458-8c00034fec4a@kernel.org> <936f151e-6951-4dea-95ed-35374ab249cf@quicinc.com> <9b3350ba-eafe-4bb0-a6cc-f1b0a06d623e@kernel.org> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 16/09/2024 10:55, Dmitry Baryshkov wrote: > On Mon, Sep 16, 2024 at 10:33:21AM GMT, Krzysztof Kozlowski wrote: >> On 13/09/2024 07:31, Taniya Das wrote: >>> >>> >>> On 8/17/2024 2:55 PM, Krzysztof Kozlowski wrote: >>>> On 16/08/2024 10:32, Taniya Das wrote: >>>>> On the QCM6490 boards the LPASS firmware controls the complete clock >>>>> controller functionalities. But the LPASS resets are required to be >>>>> controlled from the high level OS. The Audio SW driver should be able to >>>>> assert/deassert the audio resets as required. Thus in clock driver add >>>>> support for the resets. >>>>> >>>>> Signed-off-by: Taniya Das >>>>> --- >>>>> drivers/clk/qcom/lpassaudiocc-sc7280.c | 23 +++++++++++++++++++---- >>>>> 1 file changed, 19 insertions(+), 4 deletions(-) >>>>> >>>>> diff --git a/drivers/clk/qcom/lpassaudiocc-sc7280.c b/drivers/clk/qcom/lpassaudiocc-sc7280.c >>>>> index 45e726477086..b64393089263 100644 >>>>> --- a/drivers/clk/qcom/lpassaudiocc-sc7280.c >>>>> +++ b/drivers/clk/qcom/lpassaudiocc-sc7280.c >>>>> @@ -1,6 +1,7 @@ >>>>> // SPDX-License-Identifier: GPL-2.0-only >>>>> /* >>>>> * Copyright (c) 2021, The Linux Foundation. All rights reserved. >>>>> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. >>>>> */ >>>>> >>>>> #include >>>>> @@ -713,14 +714,24 @@ static const struct qcom_reset_map lpass_audio_cc_sc7280_resets[] = { >>>>> [LPASS_AUDIO_SWR_WSA_CGCR] = { 0xb0, 1 }, >>>>> }; >>>>> >>>>> +static const struct regmap_config lpass_audio_cc_sc7280_reset_regmap_config = { >>>>> + .name = "lpassaudio_cc_reset", >>>>> + .reg_bits = 32, >>>>> + .reg_stride = 4, >>>>> + .val_bits = 32, >>>>> + .fast_io = true, >>>>> + .max_register = 0xc8, >>>>> +}; >>>>> + >>>>> static const struct qcom_cc_desc lpass_audio_cc_reset_sc7280_desc = { >>>>> - .config = &lpass_audio_cc_sc7280_regmap_config, >>>>> + .config = &lpass_audio_cc_sc7280_reset_regmap_config, >>>>> .resets = lpass_audio_cc_sc7280_resets, >>>>> .num_resets = ARRAY_SIZE(lpass_audio_cc_sc7280_resets), >>>>> }; >>>>> >>>>> static const struct of_device_id lpass_audio_cc_sc7280_match_table[] = { >>>>> - { .compatible = "qcom,sc7280-lpassaudiocc" }, >>>>> + { .compatible = "qcom,qcm6490-lpassaudiocc", .data = &lpass_audio_cc_reset_sc7280_desc }, >>>> >>>> That's odd to see sc7280 reset added for qcm6490, but not used fot >>>> sc7280 at all. Didn't you mean here lpass_audio_cc_qcm6409_desc? >>>> >>>> >>> The resets descriptor(lpass_audio_cc_reset_sc7280_desc) is not part of >>> the global clock descriptor(lpass_cc_sc7280_desc) as these are part of >>> different regmaps. >>> >>> On a non-QCM6490(SC7280) boards the resets are registered after the >>> global descriptor is registered. >>> >>> But on QCM6490 board we need to register only the reset descriptor and >>> no clocks are to be handled/registered and thus passed the match data >>> for QCM6490 boards only. >> >> Yeah, but why this is sc7280? > > Because it's more or less the same HW, different TZ and hyp firmware? > Hm, ok, probably I missed something from the context. Best regards, Krzysztof