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Thu, 30 Oct 2025 05:19:46 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ThreadId: AMptcG-LwCSF Date: Thu, 30 Oct 2025 10:19:15 +0100 From: "Arnd Bergmann" To: "Ryan Chen" , "Geert Uytterhoeven" Cc: "Andrew Lunn" , BMC-SW , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Joel Stanley" , "Andrew Jeffery" , "Jeremy Kerr" , "Lee Jones" , "Catalin Marinas" , "Will Deacon" , "Bjorn Andersson" , "Nishanth Menon" , =?UTF-8?Q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , "Taniya Das" , "Lad, Prabhakar" , "Kuninori Morimoto" , "Eric Biggers" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-aspeed@lists.ozlabs.org" , "linux-kernel@vger.kernel.org" Message-Id: <80d0fb36-17d8-44c9-8941-0bac9f3b3ef2@app.fastmail.com> In-Reply-To: References: <20251022070543.1169173-1-ryan_chen@aspeedtech.com> <20251022070543.1169173-5-ryan_chen@aspeedtech.com> <6a97fbb4-19c2-4ffa-9c73-26aea02c27e4@app.fastmail.com> <71df9bdf-53b2-45e2-a9e3-5b00a556f957@lunn.ch> <01573262-69a8-44cf-ae02-2e9842c59dde@lunn.ch> <7c0c966b-c45f-47ad-9243-b945036a9bd2@app.fastmail.com> Subject: Re: [PATCH v6 4/6] arm64: dts: aspeed: Add initial AST2700 SoC device tree Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Thu, Oct 30, 2025, at 03:30, Ryan Chen wrote: >> Subject: Re: [PATCH v6 4/6] arm64: dts: aspeed: Add initial AST2700 S= oC device >> tree >> On Wed, 29 Oct 2025 at 08:26, Arnd Bergmann wrote: >> > On Wed, Oct 29, 2025, at 03:31, Ryan Chen wrote: >> > >> Subject: Re: [PATCH v6 4/6] arm64: dts: aspeed: Add initial AST2= 700 > > Thanks for pointing me in the right direction. > > After checking the TI K3 example > (https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/ti/= k3-j784s4-j742s2-common.dtsi#L75), > I see that all processing domains in that SoC share the same physical > address decoding, which makes a System-DT-style structure possible. > > However, in the AST2700 design, the Cortex-A35 (64-bit) and Cortex-M4 > (32-bit) cores each run in a distinct address space with different mem= ory > maps, so they do not share the same decode view. =20 > Because of that, a single unified .dtsi cannot directly represent both= sides > without additional translation or =E2=80=9Cranges=E2=80=9D mapping log= ic. > For example, in ca35 view uart0@14c33000, cm4 view uart0@74c33000 > From ca35 do have 0x7xxxxxxx is another peripheral decode address. This still looks like the simplest case to me, where you'd have a dtsi file describing the @soc0 and @soc1 devices using their local addresses such as uart0@c33000, and a ranges property to map it into the CPU specific physical address space, one of ranges =3D <0x0 0x0 0x0 0x14000000 0x0 0x1000000>; ranges =3D <0x0 0x0 0x0 0x74000000 0x0 0x1000000>; to remap 0x1000000 bytes (16MB) of address space from local bus addresses to one of the two clusters. This is almost what you have, except you map an entire 256MB (0x10000000) range. The exact size you want should be available in your hardware documentation. Arnd