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Tue, 23 Jun 2026 07:29:37 -0700 (PDT) From: =?UTF-8?q?Gr=C3=A9goire=20Layet?= To: joel@jms.id.au, andrew@codeconstruct.com.au, lkundrak@v3.sk, devicetree@vger.kernel.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: andrew@lunn.ch, jacky_chou@aspeedtech.com, yh_chung@aspeedtech.com, ninad@linux.ibm.com, anirudhsriniv@gmail.com, linux-serial@vger.kernel.org, linux-aspeed@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Gr=C3=A9goire=20Layet?= Subject: [PATCH v3 1/7] dt-bindings: serial: 8250: aspeed: add compatible string for ast2600 Date: Tue, 23 Jun 2026 14:25:39 +0000 Message-ID: <80d983887dfdfc7e70a6db95f8cb95b7312f3044.1782224059.git.gregoire.layet@9elements.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The ast2600 was using the ast2500 vuart compatible string. This change makes it possible to have ast2600-specific properties. Signed-off-by: Grégoire Layet --- .../devicetree/bindings/serial/8250.yaml | 20 +++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml index bb7b9c87a807..3cbd0f532e15 100644 --- a/Documentation/devicetree/bindings/serial/8250.yaml +++ b/Documentation/devicetree/bindings/serial/8250.yaml @@ -23,7 +23,9 @@ allOf: then: properties: compatible: - const: aspeed,ast2500-vuart + anyOf: + - const: aspeed,ast2500-vuart + - const: aspeed,ast2600-vuart - if: properties: compatible: @@ -287,17 +289,19 @@ properties: aspeed,sirq-polarity-sense: $ref: /schemas/types.yaml#/definitions/phandle-array description: | - Phandle to aspeed,ast2500-scu compatible syscon alongside register - offset and bit number to identify how the SIRQ polarity should be - configured. One possible data source is the LPC/eSPI mode bit. Only - applicable to aspeed,ast2500-vuart. + Phandle to aspeed,ast2500-scu or aspeed,ast2600-scu compatible syscon + alongside register offset and bit number to identify how the SIRQ + polarity should be configured. One possible data source is the LPC/eSPI + mode bit. Only applicable to aspeed,ast2500-vuart and + aspeed,ast2600-vuart. deprecated: true aspeed,lpc-io-reg: $ref: /schemas/types.yaml#/definitions/uint32-array maxItems: 1 description: | - The VUART LPC address. Only applicable to aspeed,ast2500-vuart. + The VUART LPC address. Only applicable to aspeed,ast2500-vuart and + aspeed,ast2600-vuart. aspeed,lpc-interrupts: $ref: /schemas/types.yaml#/definitions/uint32-array @@ -305,8 +309,8 @@ properties: maxItems: 2 description: | A 2-cell property describing the VUART SIRQ number and SIRQ - polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_LEVEL_HIGH). Only - applicable to aspeed,ast2500-vuart. + polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_LEVEL_HIGH). Only + applicable to aspeed,ast2500-vuart and aspeed,ast2600-vuart. required: - reg -- 2.54.0