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From: Hans Zhang <18255117159@163.com>
To: Rob Herring <robh@kernel.org>
Cc: lpieralisi@kernel.org, bhelgaas@google.com, mani@kernel.org,
	kwilczynski@kernel.org, jingoohan1@gmail.com, cassel@kernel.org,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	Hans Zhang <hans.zhang@cixtech.com>
Subject: Re: [PATCH v5 00/13] PCI: dwc: Refactor register access with dw_pcie_*_dword helper
Date: Thu, 4 Sep 2025 01:25:59 +0800	[thread overview]
Message-ID: <80da951b-674b-4092-bc9b-e5b0bac1c35e@163.com> (raw)
In-Reply-To: <CAL_JsqJ0cXB4bz+DAUq25V5suS0D-CHnujh0UyxA66UjajJO-g@mail.gmail.com>



On 2025/8/29 04:44, Rob Herring wrote:
> On Thu, Aug 28, 2025 at 9:00 AM Hans Zhang <18255117159@163.com> wrote:
>>
>> From: Hans Zhang <hans.zhang@cixtech.com>
>>
>> Register bit manipulation in DesignWare PCIe controllers currently
>> uses repetitive read-modify-write sequences across multiple drivers.
>> This pattern leads to code duplication and increases maintenance
>> complexity as each driver implements similar logic with minor variations.
>>
>> This series introduces dw_pcie_*_dword() to centralize atomic
>> register modification. The helper performs read-clear-set-write operations
>> in a single function, replacing open-coded implementations. Subsequent
>> patches refactor individual drivers to use this helper, eliminating
>> redundant code and ensuring consistent bit handling.
>>
>> The change reduces overall code size by ~350 lines while improving
>> maintainability. Each controller driver is updated in a separate
>> patch to preserve bisectability and simplify review.
> 
> If RMW functions are an improvement, then they should go in io.h. I
> don't think they are because they obfuscate the exact register
> modifications and the possible need for locking. With common API,
> anyone that understands kernel APIs will know what's going on. With a
> driver specific API, then you have to go lookup what the API does
> exactly. So I don't think this is an improvement.
> 
> Rob

Dear Rob,

Thank you very much for your reply.

My initial idea was to simplify the logic we wrote a lot of RMW under 
the DWC driver. Then I saw that there were similar well-handled codes in 
the linux kernel, so I came to do some cleaning work.


drivers/pci/access.c
int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
					u32 clear, u32 set)
{
	int ret;
	u32 val;

	ret = pcie_capability_read_dword(dev, pos, &val);
	if (ret)
		return ret;

	val &= ~clear;
	val |= set;
	return pcie_capability_write_dword(dev, pos, val);
}
EXPORT_SYMBOL(pcie_capability_clear_and_set_dword);


include/linux/pci.h
static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
					    u32 set)
{
	return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
}

static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
					      u32 clear)
{
	return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
}



And the subsequent introduced API: Personally, I think they are very 
valuable for reference. Of course, it depends on the final opinions of 
the maintainer and all of you.

drivers/pci/access.c
void pci_clear_and_set_config_dword(const struct pci_dev *dev, int pos,
				    u32 clear, u32 set)
{
	u32 val;

	pci_read_config_dword(dev, pos, &val);
	val &= ~clear;
	val |= set;
	pci_write_config_dword(dev, pos, val);
}
EXPORT_SYMBOL(pci_clear_and_set_config_dword);



Best regards,
Hans


      reply	other threads:[~2025-09-03 17:26 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-28 13:59 Hans Zhang
2025-08-28 13:59 ` [PATCH v5 01/13] PCI: dwc: Add dw_pcie_*_dword() for register bit manipulation Hans Zhang
2025-08-28 13:59 ` [PATCH v5 02/13] PCI: dwc: Refactor code by using dw_pcie_*_dword() Hans Zhang
2025-08-28 13:59 ` [PATCH v5 03/13] PCI: dra7xx: " Hans Zhang
2025-08-28 13:59 ` [PATCH v5 04/13] PCI: imx6: " Hans Zhang
2025-08-28 13:59 ` [PATCH v5 05/13] PCI: meson: " Hans Zhang
2025-08-28 13:59 ` [PATCH v5 06/13] PCI: armada8k: " Hans Zhang
2025-08-28 13:59 ` [PATCH v5 07/13] PCI: bt1: " Hans Zhang
2025-08-28 13:59 ` [PATCH v5 08/13] PCI: dw-rockchip: " Hans Zhang
2025-08-28 13:59 ` [PATCH v5 09/13] PCI: fu740: " Hans Zhang
2025-08-28 13:59 ` [PATCH v5 10/13] PCI: qcom: " Hans Zhang
2025-08-28 13:59 ` [PATCH v5 11/13] PCI: qcom-ep: " Hans Zhang
2025-08-28 13:59 ` [PATCH v5 12/13] PCI: rcar-gen4: " Hans Zhang
2025-08-28 13:59 ` [PATCH v5 13/13] PCI: tegra194: " Hans Zhang
2025-08-28 20:44 ` [PATCH v5 00/13] PCI: dwc: Refactor register access with dw_pcie_*_dword helper Rob Herring
2025-09-03 17:25   ` Hans Zhang [this message]

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