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[78.26.46.173]) by smtp.gmail.com with ESMTPSA id k14-20020ac257ce000000b0048a7fa5bff1sm2534024lfo.248.2022.07.27.05.36.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 27 Jul 2022 05:37:00 -0700 (PDT) Message-ID: <80f08089-e3bb-983e-313b-45613364829e@linaro.org> Date: Wed, 27 Jul 2022 14:36:59 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.12.0 Subject: Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK Content-Language: en-US To: Biju Das , "Lad, Prabhakar" Cc: Prabhakar Mahadev Lad , Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Linux-Renesas , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , linux-riscv , LKML References: <20220726180623.1668-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20220726180623.1668-5-prabhakar.mahadev-lad.rj@bp.renesas.com> <636e9214-4b36-e9a6-3c6b-b6edb944335e@linaro.org> <9f32a4a9-66b4-ba2e-1713-436103c2faf8@linaro.org> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 27/07/2022 14:21, Biju Das wrote: > Hi, > >> Subject: Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding >> documentation for Renesas RZ/Five SoC and SMARC EVK >> >> On 27/07/2022 13:37, Lad, Prabhakar wrote: >>>>>> >>>>> I did run the dtbs_check test as per your suggestion (below is the >>>>> log) and didn't see "no matching schema error" >>>>> >>>> >>>> So you do not see any errors at all. Then it does not work, does it? >>>> >>> Right I reverted my changes I can see it complaining, dtb_check seems >>> to have returned false positive in my case. >>> >>> What approach would you suggest to ignore the schema here? >> >> I don't think currently it would work with your approach. Instead, you >> should select here all SoCs which the schema should match. >> >> This leads to my previous concern - you use the same SoC compatible for >> two different architectures and different SoCs: ARMv8 and RISC-V. > > Or is it same SoC(R9A07G043) based on two different CPU architectures (ARMv8 and RISC-V) Then it is not the same SoC! Same means same, identical. CPU architecture is one of the major differences, which means it is not the same. > Using same SoM and Carrier board? It's like saying PC with x86 and ARMv8 board are the same because they both use same "PC chassis". Best regards, Krzysztof