Re: [PATCH 5/9] dt-bindings: interrupt-controller: Add MIPS P8700 ACLINT MSWI

[Aleksa Paunovic <aleksa.paunovic@htecgroup.com>]

Hi Conor,

On 9/15/26 20:15, Conor Dooley wrote:
> On Mon, Sep 14, 2026 at 03:55:53PM +0200, Aleksa Paunovic via B4 Relay wrote:
>> From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
>>
>> Document the aclint mswi compatible for the MIPS P8700 and
>> introduce the 'riscv,hart-indexes' property,
>> used to address the sparse MIPS P8700 harts.
>>
>> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
>> ---
>>  .../thead,c900-aclint-mswi.yaml                    | 34 ++++++++++++++++++++++
>>  1 file changed, 34 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
>> index 62fd220e126e650e3800d8eee2a749fdbbde6108..47c04943eb0c793467aaa5570776605cae0eadfd 100644
>> --- a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
>> +++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
>> @@ -17,6 +17,8 @@ properties:
>>                - sophgo,sg2042-aclint-mswi
>>                - sophgo,sg2044-aclint-mswi
>>            - const: thead,c900-aclint-mswi
>> +      - items:
>> +          - const: gf,mips-p8700-aclint-mswi
>>        - items:
>>            - enum:
>>                - anlogic,dr1v90-aclint-mswi
>> @@ -29,6 +31,14 @@ properties:
>>      minItems: 1
>>      maxItems: 4095
>>  
>> +  riscv,hart-indexes:
> Nothing in this binding is a ratified extension, despite how prevalent
> the use has become, so I object to using riscv as a prefix for something
> the other devices don't use.
I can drop the property in v2. There's no reader in Linux, OpenSBI or U-Boot as far as I can tell. 

Best regards,
Aleksa