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dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=altera.com; Received: from SJ0PR03MB5950.namprd03.prod.outlook.com (2603:10b6:a03:2d3::20) by BY5PR03MB5281.namprd03.prod.outlook.com (2603:10b6:a03:226::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.546.22; Thu, 29 Oct 2026 06:21:17 +0000 Received: from SJ0PR03MB5950.namprd03.prod.outlook.com ([fe80::53a0:bf93:6b6b:de01]) by SJ0PR03MB5950.namprd03.prod.outlook.com ([fe80::53a0:bf93:6b6b:de01%5]) with mapi id 15.21.0522.017; Thu, 29 Oct 2026 06:21:17 +0000 Message-ID: <80fd1113-88a0-444c-ab2c-6ea880e39c87@altera.com> Date: Thu, 29 Oct 2026 14:21:04 +0800 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/4] dt-bindings: mmc: cdns,sd6hc: add SD6HC DDR50 read-path tuning To: Krzysztof Kozlowski Cc: Tanmay Kathpalia , Adrian Hunter , linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org References: <5ea5d406b527cb9b7015693191c9bdeb9202a1bc.1791459448.git.tze.yee.ng@altera.com> <20261012-futuristic-worm-of-camouflage-cc2e3e@quoll> Content-Language: en-US From: "NG, TZE YEE" In-Reply-To: <20261012-futuristic-worm-of-camouflage-cc2e3e@quoll> Content-Type: text/plain; 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Why making it difficult for us? > Sorry for the friction, that was my mistake. I'll switch to b4 for v3 so the series carries a stable change-id and the cover letter links back to the earlier versions, and b4 diff works for you. >> --- >> .../devicetree/bindings/mmc/cdns,sd6hc.yaml | 30 +++++++++++++++++++ >> 1 file changed, 30 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/mmc/cdns,sd6hc.yaml b/Documentation/devicetree/bindings/mmc/cdns,sd6hc.yaml >> index d5ea2717904b..911ce58f8dab 100644 >> --- a/Documentation/devicetree/bindings/mmc/cdns,sd6hc.yaml >> +++ b/Documentation/devicetree/bindings/mmc/cdns,sd6hc.yaml >> @@ -74,6 +74,36 @@ properties: >> maximum: 1000 >> default: 24 >> >> + cdns,ddr-read-dqs-delay-ps: >> + description: > >> + Read-DQS delay (DLL_SLAVE[7:0]) in picoseconds that centres the read >> + eye in the extended-read DDR modes (SD DDR50, eMMC DDR52), which have >> + no CMD19 tuning. The PHY runs the DLL bypassed in these modes, so the >> + driver converts this to delay elements (divided by >> + cdns,delay-element-ps). The 8-bit field holds at most 255 elements; >> + larger values are clamped to that limit. >> + minimum: 0 > > Drop, 0 is the default. > Will drop it in v3. > Where is the maximum value? > The value is in ps, but the register (DLL_SLAVE[7:0]) counts delay elements, so the driver divides by cdns,delay-element-ps and clamps to the 8-bit field. There is therefore no fixed ps maximum, the real limit is 255 * cdns,delay-element-ps, which varies with that property. Rather than pick an arbitrary ps cap, I'd prefer to express this property directly as the delay-element count the field holds: cdns,ddr-read-dqs-delay: 0..255 (DLL delay elements, each element cdns,delay-element-ps wide) That maps 1:1 to the hardware field, gives a clean maximum: 255, and the element size is already described by cdns,delay-element-ps. Would that be acceptable, or would you rather keep picoseconds with a fixed cap (e.g. ~one DDR50 bit period, 50MHz = 20ns = 20000 ps)? >> + default: 0 >> + >> + cdns,ddr-no-lpbk-dqs: >> + description: > > > Drop > everywhere > Will drop > in v3. I'll use plain "description:" on all three new properties. > Best regards, > Krzysztof Thanks, Tze Yee