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dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amlogic.com; Received: from TYZPR03MB5743.apcprd03.prod.outlook.com (2603:1096:400:74::7) by TY8PR03MB10498.apcprd03.prod.outlook.com (2603:1096:405:3ab::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.592.8; Wed, 4 Nov 2026 02:56:56 +0000 Received: from TYZPR03MB5743.apcprd03.prod.outlook.com ([fe80::7f51:5771:90c4:8c40]) by TYZPR03MB5743.apcprd03.prod.outlook.com ([fe80::7f51:5771:90c4:8c40%3]) with mapi id 15.21.0569.011; Wed, 4 Nov 2026 02:56:56 +0000 Message-ID: <811e78bf-7d5c-43ad-885d-0573e25e3d81@amlogic.com> Date: Wed, 4 Nov 2026 10:56:51 +0800 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/2] dt-bindings: i3c: silvaco,i3c-master: Add Amlogic A9 support To: Krzysztof Kozlowski Cc: Alexandre Belloni , Frank Li , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Miquel Raynal , Kees Cook , "Gustavo A. R. Silva" , linux-i3c@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, imx@lists.linux.dev, linux-hardening@vger.kernel.org, xianwei.zhao@amlogic.com, Kelvin.Zhang@amlogic.com References: <20261102-a9_i3c-v2-0-0c474bfccffa@amlogic.com> <20261102-a9_i3c-v2-2-0c474bfccffa@amlogic.com> <20261103-emotional-objective-jaybird-0627b5@quoll> Content-Language: en-GB From: Junyi Zhao In-Reply-To: <20261103-emotional-objective-jaybird-0627b5@quoll> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: JH0PR04CA0002.apcprd04.prod.outlook.com (2603:1096:990:4::6) To TYZPR03MB5743.apcprd03.prod.outlook.com (2603:1096:400:74::7) X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYZPR03MB5743:EE_|TY8PR03MB10498:EE_ X-MS-Office365-Filtering-Correlation-Id: 140244b6-20c0-447a-66a6-08df3a1f4982 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|7416014|376014|366016|1800799024|6133799003|10067099003|18002099003|22082099003|56012099006|11063799006|4143699003|261022105027099003|261028144727099003|261026140227099003|261026121527099003|261021121427099003|261102123227099003; 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On 03/11/2026 19:42, Krzysztof Kozlowski wrote: > [ EXTERNAL EMAIL ] > > On Mon, Nov 02, 2026 at 07:05:40PM +0800, Junyi Zhao wrote: >> Amlogic A9 SoCs integrate the Silvaco I3C IP with two controller >> instances: >> >> - amlogic,a9-i3c for the EE domain, which takes two clocks, >> "pclk" and "fast_clk" like the NXP variants; >> >> - amlogic,a9-ao-i3c for the Always-On (AO) domain, which exposes >> only "pclk": its bus clock is generated by an internal divider >> located in the controller's own register space. >> >> Allow both compatibles with the "silvaco,i3c-master-v1" fallback and >> enforce the per-variant clock counts. > > This we see in the diff, but we do not see WHY. i will add a description of the I3C peripheral integratation detail at hardware-level. > > Best regards, > Krzysztof >