From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Tao Zhang <quic_taozha@quicinc.com>,
Mathieu Poirier <mathieu.poirier@linaro.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Konrad Dybcio <konradybcio@gmail.com>,
Mike Leach <mike.leach@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Jinlong Mao <quic_jinlmao@quicinc.com>,
Leo Yan <leo.yan@linaro.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
Tingwei Zhang <quic_tingweiz@quicinc.com>,
Yuanfang Zhang <quic_yuanfang@quicinc.com>,
Trilok Soni <quic_tsoni@quicinc.com>,
Song Chai <quic_songchai@quicinc.com>,
linux-arm-msm@vger.kernel.org, andersson@kernel.org
Subject: Re: [PATCH v5 05/10] coresight-tpda: Add support to configure CMB element
Date: Thu, 1 Feb 2024 10:26:40 +0000 [thread overview]
Message-ID: <812bd339-4728-40ee-b19e-c8a04cc740de@arm.com> (raw)
In-Reply-To: <9fca774e-3519-4d0c-ba61-6b84965f36c2@quicinc.com>
On 01/02/2024 02:25, Tao Zhang wrote:
>
> On 1/31/2024 6:02 PM, Suzuki K Poulose wrote:
>> On 31/01/2024 01:39, Tao Zhang wrote:
>>>
>>> On 1/30/2024 8:35 PM, Suzuki K Poulose wrote:
>>>> On 30/01/2024 09:02, Tao Zhang wrote:
>>>>> Read the CMB element size from the device tree. Set the register
>>>>> bit that controls the CMB element size of the corresponding port.
>>>>>
>>>>> Reviewed-by: James Clark <james.clark@arm.com>
>>>>> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
>>>>> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
>>>>> ---
>>>>> drivers/hwtracing/coresight/coresight-tpda.c | 123
>>>>> +++++++++++--------
>>>>> drivers/hwtracing/coresight/coresight-tpda.h | 6 +
>>>>> 2 files changed, 79 insertions(+), 50 deletions(-)
>>>>>
>>>>> diff --git a/drivers/hwtracing/coresight/coresight-tpda.c
>>>>> b/drivers/hwtracing/coresight/coresight-tpda.c
>>>>> index 4ac954f4bc13..fcddff3ded81 100644
>>>>> --- a/drivers/hwtracing/coresight/coresight-tpda.c
>>>>> +++ b/drivers/hwtracing/coresight/coresight-tpda.c
>>>>> @@ -18,6 +18,7 @@
>>>>> #include "coresight-priv.h"
>>>>> #include "coresight-tpda.h"
>>>>> #include "coresight-trace-id.h"
>>>>> +#include "coresight-tpdm.h"
>>>>> DEFINE_CORESIGHT_DEVLIST(tpda_devs, "tpda");
>>>>> @@ -28,24 +29,57 @@ static bool coresight_device_is_tpdm(struct
>>>>> coresight_device *csdev)
>>>>> CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM);
>>>>> }
>>>>> +static void tpdm_clear_element_size(struct coresight_device *csdev)
>>>>> +{
>>>>> + struct tpda_drvdata *drvdata =
>>>>> dev_get_drvdata(csdev->dev.parent);
>>>>> +
>>>>> + drvdata->dsb_esize = 0;
>>>>> + drvdata->cmb_esize = 0;
>>>>> +}
>>>>> +
>>>>> +static void tpda_set_element_size(struct tpda_drvdata *drvdata,
>>>>> u32 *val)
>>>>> +{
>>>>> +
>>>>
>>>>
>>>>
>>>>> + if (drvdata->dsb_esize == 64)
>>>>> + *val |= TPDA_Pn_CR_DSBSIZE;
>>>>
>>>> We don't seem to be clearing the fields we modify, before updating
>>>> them. This may be OK in real world where the device connected to
>>>> TPDA port
>>>> may not change. But it is always safer to clear the bits and set it.
>>>>
>>>> e.g.:
>>>> *val &= ~(TPDA_Pn_CR_DSBSIZE | TPDA_Pn_CR_CMBSIZE);
>>>>
>>>>
>>>>
>>>>> + else if (drvdata->dsb_esize == 32)
>>>>> + *val &= ~TPDA_Pn_CR_DSBSIZE;
>>>>> +
>>>>> + if (drvdata->cmb_esize == 64)
>>>>> + *val |= FIELD_PREP(TPDA_Pn_CR_CMBSIZE, 0x2);
>>>>> + else if (drvdata->cmb_esize == 32)
>>>>> + *val |= FIELD_PREP(TPDA_Pn_CR_CMBSIZE, 0x1);
>>>>
>>>> Similarly here ^^^. I am happy to fix it up if you are OK with it
>>>> (unless there are other changes that need a respin)
>>>
>>> Thank you. I would be very grateful if you could help for this.
>>
>> Given, you need to respin, please incorporate this change too.
>
> Sure.
>
> Is it OK if I modify the code as follow and update to this patch directly?
>
> *val &= ~(TPDA_Pn_CR_DSBSIZE | TPDA_Pn_CR_CMBSIZE);
>
> if (drvdata->dsb_esize == 64)
> *val |= TPDA_Pn_CR_DSBSIZE;
> else if (drvdata->dsb_esize == 32)
> *val &= ~TPDA_Pn_CR_DSBSIZE;
>
> if (drvdata->cmb_esize == 64)
> *val |= FIELD_PREP(TPDA_Pn_CR_CMBSIZE, 0x2);
> else if (drvdata->cmb_esize == 32)
> *val |= FIELD_PREP(TPDA_Pn_CR_CMBSIZE, 0x1);.
> else if (drvdata->cmb_esize == 8)
> *val &= ~TPDA_Pn_CR_CMBSIZE;
Yes, that looks good to me. Even though you would be clearing the fields
for (DSB=32 and CMB=8) once again, it is good to leave it like that
rather than skipping them, making people stare at it to figure out if
this was correct or not.
Suzuki
>
> Best,
>
> Tao
>
>>
>> Suzuki
>>
>>
>>
next prev parent reply other threads:[~2024-02-01 10:26 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-30 9:02 [PATCH v5 00/10] Add support to configure TPDM CMB subunit Tao Zhang
2024-01-30 9:02 ` [PATCH v5 01/10] coresight-tpdm: Optimize the store function of tpdm simple dataset Tao Zhang
2024-01-30 9:02 ` [PATCH v5 02/10] coresight-tpdm: Optimize the useage of tpdm_has_dsb_dataset Tao Zhang
2024-01-30 9:02 ` [PATCH v5 03/10] dt-bindings: arm: qcom,coresight-tpdm: Add support for CMB element size Tao Zhang
2024-01-31 7:42 ` Krzysztof Kozlowski
2024-01-30 9:02 ` [PATCH v5 04/10] coresight-tpdm: Add CMB dataset support Tao Zhang
2024-01-30 9:02 ` [PATCH v5 05/10] coresight-tpda: Add support to configure CMB element Tao Zhang
2024-01-30 12:35 ` Suzuki K Poulose
2024-01-31 1:39 ` Tao Zhang
2024-01-31 10:02 ` Suzuki K Poulose
2024-02-01 2:25 ` Tao Zhang
2024-02-01 10:26 ` Suzuki K Poulose [this message]
2024-01-30 9:02 ` [PATCH v5 06/10] coresight-tpdm: Add support to configure CMB Tao Zhang
2024-01-30 9:02 ` [PATCH v5 07/10] coresight-tpdm: Add pattern registers support for CMB Tao Zhang
2024-01-30 12:40 ` Suzuki K Poulose
2024-01-31 1:12 ` Tao Zhang
2024-01-30 9:02 ` [PATCH v5 08/10] coresight-tpdm: Add timestamp control register support for the CMB Tao Zhang
2024-01-30 12:42 ` Suzuki K Poulose
2024-01-31 1:12 ` Tao Zhang
2024-01-30 9:02 ` [PATCH v5 09/10] dt-bindings: arm: qcom,coresight-tpdm: Add support for TPDM CMB MSR register Tao Zhang
2024-01-30 9:02 ` [PATCH v5 10/10] coresight-tpdm: Add msr register support for CMB Tao Zhang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=812bd339-4728-40ee-b19e-c8a04cc740de@arm.com \
--to=suzuki.poulose@arm.com \
--cc=alexander.shishkin@linux.intel.com \
--cc=andersson@kernel.org \
--cc=coresight@lists.linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=gregkh@linuxfoundation.org \
--cc=konradybcio@gmail.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=leo.yan@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mathieu.poirier@linaro.org \
--cc=mike.leach@linaro.org \
--cc=quic_jinlmao@quicinc.com \
--cc=quic_songchai@quicinc.com \
--cc=quic_taozha@quicinc.com \
--cc=quic_tingweiz@quicinc.com \
--cc=quic_tsoni@quicinc.com \
--cc=quic_yuanfang@quicinc.com \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®