From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753302AbcI1LUK (ORCPT ); Wed, 28 Sep 2016 07:20:10 -0400 Received: from bear.ext.ti.com ([198.47.19.11]:35752 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753199AbcI1LUB (ORCPT ); Wed, 28 Sep 2016 07:20:01 -0400 Subject: Re: [PATCH] drm: tilcdc: add a workaround for failed clk_set_rate() To: Bartosz Golaszewski , Jyri Sarha References: <1474990196-808-1-git-send-email-bgolaszewski@baylibre.com> CC: David Airlie , Kevin Hilman , Michael Turquette , linux-drm , LKML From: Tomi Valkeinen Message-ID: <8136a79b-23b8-d353-8602-428cc20947f6@ti.com> Date: Wed, 28 Sep 2016 14:19:53 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 MIME-Version: 1.0 In-Reply-To: <1474990196-808-1-git-send-email-bgolaszewski@baylibre.com> Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="btH0FM7qtxuRPBtkI62WQEoALrLLKC7CP" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --btH0FM7qtxuRPBtkI62WQEoALrLLKC7CP Content-Type: multipart/mixed; boundary="ND3RqV80GQjaLubGmL4W0kc1vPkpXgDLS"; protected-headers="v1" From: Tomi Valkeinen To: Bartosz Golaszewski , Jyri Sarha Cc: David Airlie , Kevin Hilman , Michael Turquette , linux-drm , LKML Message-ID: <8136a79b-23b8-d353-8602-428cc20947f6@ti.com> Subject: Re: [PATCH] drm: tilcdc: add a workaround for failed clk_set_rate() References: <1474990196-808-1-git-send-email-bgolaszewski@baylibre.com> In-Reply-To: <1474990196-808-1-git-send-email-bgolaszewski@baylibre.com> --ND3RqV80GQjaLubGmL4W0kc1vPkpXgDLS Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Hi, On 27/09/16 18:29, Bartosz Golaszewski wrote: > Some architectures don't use the common clock framework and don't > implement all the clk interfaces for every clock. This is the case > for da850-lcdk where clk_set_rate() only works for PLL0 and PLL1. >=20 > Trying to set the clock rate for the LCDC clock results in -EINVAL > being returned. >=20 > As a workaround for that: if the call to clk_set_rate() fails, fall > back to adjusting the clock divider instead. Proper divider value is > calculated by dividing the current clock rate by the required pixel > clock rate in HZ. >=20 > This code is based on a hack initially developed internally for > baylibre by Karl Beldan . >=20 > Tested with a da850-lcdk with an LCD display connected over VGA. >=20 > Signed-off-by: Bartosz Golaszewski > --- > drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 31 ++++++++++++++++++++++++----= --- > 1 file changed, 24 insertions(+), 7 deletions(-) >=20 > diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c b/drivers/gpu/drm/til= cdc/tilcdc_crtc.c > index 2087689..f2ff3b1 100644 > --- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c > +++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c > @@ -636,22 +636,40 @@ void tilcdc_crtc_update_clk(struct drm_crtc *crtc= ) > struct drm_device *dev =3D crtc->dev; > struct tilcdc_drm_private *priv =3D dev->dev_private; > unsigned long lcd_clk; > - const unsigned clkdiv =3D 2; /* using a fixed divider of 2 */ > + unsigned int clkdiv; > int ret; > =20 > pm_runtime_get_sync(dev->dev); > =20 > tilcdc_crtc_disable(crtc); > =20 > + clkdiv =3D 2; /* first try using a standard divider of 2 */ > + > /* mode.clock is in KHz, set_rate wants parameter in Hz */ > ret =3D clk_set_rate(priv->clk, crtc->mode.clock * 1000 * clkdiv); > + lcd_clk =3D clk_get_rate(priv->clk); > if (ret < 0) { > - dev_err(dev->dev, "failed to set display clock rate to: %d\n", > - crtc->mode.clock); > - goto out; > - } > + /* > + * If we fail to set the clock rate (some architectures don't > + * use the common clock framework yet and may not implement > + * all the clk API calls for every clock), try the next best > + * thing: adjusting the clock divider, unless clk_get_rate() > + * failed as well. > + */ > + dev_err(dev->dev, > + "failed to set display clock rate to: %d\n", > + crtc->mode.clock); This code path is not an error, is it? No reason to print anything here. > + if (!lcd_clk) { > + /* Nothing more we can do. Just bail out. */ > + dev_err(dev->dev, > + "failed to read the display clock rate\n"); This is an error, but maybe the error message should say something else. I mean, "failed to _read_ display clk rate", when the user tries to set pixel clock, doesn't quite make sense =3D). > + goto out; > + } > =20 > - lcd_clk =3D clk_get_rate(priv->clk); > + dev_info(dev->dev, > + "falling back to adjusting the clock divisor\n"); I don't see a reason for this print either. This is normal if the platform doesn't support changing the lcdc's input clock. > + clkdiv =3D DIV_ROUND_CLOSEST(lcd_clk, (crtc->mode.clock * 1000)); > + } If the clock divider path easily creates pixel clocks that are quite far from the requested ones (which I think it does), I think it would make sense to have a print here if the final pixel clock is far enough from the requested one. And that's a valid print for the current code path too, as it's not clear whether lcdc's input clock can be set to an exact value. > DBG("lcd_clk=3D%lu, mode clock=3D%d, div=3D%u", > lcd_clk, crtc->mode.clock, clkdiv); > @@ -664,7 +682,6 @@ void tilcdc_crtc_update_clk(struct drm_crtc *crtc) > tilcdc_set(dev, LCDC_CLK_ENABLE_REG, > LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN | > LCDC_V2_CORE_CLK_EN); > - Extra change here. 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