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Mon, 09 Nov 2026 08:27:33 -0800 (PST) Received: from [192.168.1.3] ([37.18.141.193]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-49597e0097dsm11053891f8f.57.2026.11.09.08.27.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 09 Nov 2026 08:27:32 -0800 (PST) Message-ID: <8136ec16-8132-4212-8ccc-6aff05ab698c@linaro.org> Date: Mon, 9 Nov 2026 16:27:31 +0000 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 06/23] coresight: trbe: Drop redundant disable from enable path To: Leo Yan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, coresight@lists.linaro.org, Suzuki K Poulose , Mike Leach , Alexander Shishkin , Anshuman Khandual , Tamas Petz , Tamas Zsoldos , Suyash Mahar , Amir Ayupov References: <20261016-trbe_enable_disable_irq_handle_refactor-v2-0-3f57cf3199b1@arm.com> <20261016-trbe_enable_disable_irq_handle_refactor-v2-6-3f57cf3199b1@arm.com> Content-Language: en-US From: James Clark In-Reply-To: <20261016-trbe_enable_disable_irq_handle_refactor-v2-6-3f57cf3199b1@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 16/10/2026 17:55, Leo Yan wrote: > The Arm ARM (ARM DDI 0487 M.c) rule RDJMDD says: > > | When the following conditions apply, the PE might ignore a direct or > | external write to any of certain Trace Buffer Unit registers, other > | than a direct write or external write to TRBLIMITR_EL1 that clears > | the conditions: > | • TRBLIMITR_EL1.E is 1, and either FEAT_TRBE_EXT is not implemented > | or the Trace Buffer Unit is using Self-hosted mode. > Doesn't the rule just say that the buffer must be disabled before doing writes to other registers? But the explanation for removing the extra disable is that it's already disabled at this point, so nothing changes. The commit message would be clearer without this bit IMO. There's no architectural requirement to make this change, it's only a software one. Otherwise: Reviewed-by: James Clark > trbe_enable_hw() calls set_trbe_disabled() first to ensure TRBE has > already been disabled before programming any other TRBE registers. > > However, TRBE is already expected to be disabled before trbe_enable_hw() > runs: > > 1. CPU probe resets TRBLIMITR_EL1 via trbe_reset_local(); > 2. Interrupt handling disables the buffer before re-enabling it; > 3. The normal disable path clears TRBLIMITR_EL1.E. > > Calling set_trbe_disabled() from the enable path is therefore redundant. > Drop the call from trbe_enable_hw(), which only needs to program a > known-disabled TRBE. > > Signed-off-by: Leo Yan > --- > drivers/hwtracing/coresight/coresight-trbe.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c > index a7c1037a048f5236598f8f3a7cc4f47bff9d329c..979d0fa84c1c7b448c1ce5cd7a37dff8845795ef 100644 > --- a/drivers/hwtracing/coresight/coresight-trbe.c > +++ b/drivers/hwtracing/coresight/coresight-trbe.c > @@ -652,7 +652,6 @@ static void trbe_enable_hw(struct trbe_buf *buf) > WARN_ON(buf->trbe_hw_base < buf->trbe_base); > WARN_ON(buf->trbe_write < buf->trbe_hw_base); > WARN_ON(buf->trbe_write >= buf->trbe_limit); > - set_trbe_disabled(buf->cpudata); > clr_trbe_status(); > set_trbe_base_pointer(buf->trbe_hw_base); > set_trbe_write_pointer(buf->trbe_write); >