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Mon, 26 Feb 2024 09:56:42 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 41Q9ufB5022364 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 26 Feb 2024 09:56:41 GMT Received: from [10.201.2.96] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Mon, 26 Feb 2024 01:56:37 -0800 Message-ID: <8144cb83-077d-46ec-ae10-13d99fba34ae@quicinc.com> Date: Mon, 26 Feb 2024 15:26:34 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/3] clk: qcom: gcc-ipq5018: fix 'halt_reg' offset of 'gcc_pcie1_pipe_clk' Content-Language: en-US To: Gabor Juhos , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , "Gokul Sriram Palanisamy" , Varadarajan Narayanan , Sricharan Ramabadhran CC: , , References: <20240225-gcc-ipq5018-register-fixes-v1-0-3c191404d9f0@gmail.com> <20240225-gcc-ipq5018-register-fixes-v1-2-3c191404d9f0@gmail.com> From: Kathiravan Thirumoorthy In-Reply-To: <20240225-gcc-ipq5018-register-fixes-v1-2-3c191404d9f0@gmail.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: F-0P-0eFBI0TIKNWrJbtHzkldxBZFZTB X-Proofpoint-GUID: F-0P-0eFBI0TIKNWrJbtHzkldxBZFZTB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-26_07,2024-02-23_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 suspectscore=0 phishscore=0 adultscore=0 bulkscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2402260074 On 2/25/2024 11:02 PM, Gabor Juhos wrote: > The following table shows the values of the 'halt_reg' and the > 'enable_reg' fields from the pcie clocks defined in the current > driver: > > clock halt_reg enable_reg > > gcc_pcie0_ahb_clk 0x75010 0x75010 > gcc_pcie0_aux_clk 0x75014 0x75014 > gcc_pcie0_axi_m_clk 0x75008 0x75008 > gcc_pcie0_axi_s_bridge_clk 0x75048 0x75048 > gcc_pcie0_axi_s_clk 0x7500c 0x7500c > gcc_pcie0_pipe_clk 0x75018 0x75018 > > gcc_pcie1_ahb_clk 0x76010 0x76010 > gcc_pcie1_aux_clk 0x76014 0x76014 > gcc_pcie1_axi_m_clk 0x76008 0x76008 > gcc_pcie1_axi_s_bridge_clk 0x76048 0x76048 > gcc_pcie1_axi_s_clk 0x7600c 0x7600c > gcc_pcie1_pipe_clk 8* 0x76018 > > Based on the table, it is quite likely that the pcie0 and the pci1 > clocks are using the same register layout, however it seems that > the value of the 'halt_reg' field in the 'gcc_pcie1_pipe_clk' clock > is wrong. > > In the downstream driver [1], the same '0x76018' value is used for > both the 'halt_reg' and for the 'enable_reg' fields of the > 'gcc_pcie1_pipe_clk' clock. > > Update the current driver to use the same value used downstream as > probably that is the correct value. > > 1. https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4.r4/drivers/clk/qcom/gcc-ipq5018.c?ref_type=heads#L2316 Reviewed-by: Kathiravan Thirumoorthy > > Fixes: e3fdbef1bab8 ("clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018") > Signed-off-by: Gabor Juhos > --- > drivers/clk/qcom/gcc-ipq5018.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c > index cef9a1e7c9fdb..5e81cfa77293a 100644 > --- a/drivers/clk/qcom/gcc-ipq5018.c > +++ b/drivers/clk/qcom/gcc-ipq5018.c > @@ -2180,7 +2180,7 @@ static struct clk_branch gcc_pcie1_axi_s_clk = { > }; > > static struct clk_branch gcc_pcie1_pipe_clk = { > - .halt_reg = 8, > + .halt_reg = 0x76018, > .halt_check = BRANCH_HALT_DELAY, > .halt_bit = 31, > .clkr = { >