From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0FE78C43461 for ; Tue, 8 Sep 2020 16:36:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C028D206E7 for ; Tue, 8 Sep 2020 16:36:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="u5cgThpU" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731514AbgIHQgI (ORCPT ); Tue, 8 Sep 2020 12:36:08 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:51706 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732026AbgIHQcF (ORCPT ); Tue, 8 Sep 2020 12:32:05 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 088Ewtci011590; Tue, 8 Sep 2020 09:58:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1599577135; bh=fKarsEyMOJcKTwtf5n0tGq73QBl/jjsYYqxZnKWLtfU=; h=Subject:From:To:CC:References:Date:In-Reply-To; b=u5cgThpU3AlHzuETTDonZHqMfFUtNgZRBjQwQyWHhuJeOoNft0cOIeqIVbic0RiB7 JvMJ80lOItnioC30vw/zZJU6VnY303X8j/ZkIqIZ0T2otDT/oYoekdZHQJC3wYPGEa UqbCO2fBUSWG8TEtgpZNpcBy843k6qnVy/gatlt8= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 088EwtaO121227 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Sep 2020 09:58:55 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 8 Sep 2020 09:58:55 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 8 Sep 2020 09:58:55 -0500 Received: from [10.250.38.37] (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 088EwtuK053861; Tue, 8 Sep 2020 09:58:55 -0500 Subject: Re: [PATCH 2/2] ASoC: tlv320adcx140: Wake up codec before accessing register From: Dan Murphy To: Camel Guo , , , CC: , , , Camel Guo References: <20200908083521.14105-1-camel.guo@axis.com> <20200908083521.14105-2-camel.guo@axis.com> <89f8cce0-2407-15f5-a8e5-0aa17a2eb2c4@ti.com> Message-ID: <8160bf81-a72d-2db0-0767-79b0509ff143@ti.com> Date: Tue, 8 Sep 2020 09:58:55 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <89f8cce0-2407-15f5-a8e5-0aa17a2eb2c4@ti.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Camel On 9/8/20 6:49 AM, Dan Murphy wrote: > Camel > > On 9/8/20 3:35 AM, Camel Guo wrote: >> From: Camel Guo >> >> According to its datasheet, after reset this codec goes into sleep >> mode. In this mode, any register accessing should be avoided except for >> exiting sleep mode. Hence this commit moves SLEEP_CFG access before any >> register accessing. > > This is interesting because our HW team suggested putting the device > into sleep mode when doing register writes/reads because they were > finding abnormalities in the register settings when the device is active. > > I have a local patch that changes this as well that the HW team > requested. OK I have clarification on this now.  Their original request was incorrect they indicate the BIAS, ADC and PLLs be powered down during writes and reads. > > Mark > > Let me run this by the HW team first before applying this patch. Mark Acked-by: Dan Murphy > > Dan >