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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b87023a8a33sm538070066b.18.2026.01.12.03.29.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 12 Jan 2026 03:29:29 -0800 (PST) Message-ID: <816456c5-ad32-4829-ae0d-a0d09f468863@oss.qualcomm.com> Date: Mon, 12 Jan 2026 12:29:26 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/5] PCI: dwc: Add support for retaining link during host init To: Bjorn Helgaas , Krishna Chaitanya Chundru Cc: Vinod Koul , Neil Armstrong , Philipp Zabel , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org References: <20260109155350.GA546142@bhelgaas> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260109155350.GA546142@bhelgaas> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: DOcJxpxVAcm0xgUCpDQub0giuSMBD6rO X-Authority-Analysis: v=2.4 cv=ZuDg6t7G c=1 sm=1 tr=0 ts=6964db1b cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=sQDjRcaqkbB8EtgPkRQA:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-ORIG-GUID: DOcJxpxVAcm0xgUCpDQub0giuSMBD6rO X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTEyMDA5MSBTYWx0ZWRfX7ypuwKJFhC9W 75McALqerbGF+PZGMGqr0uMf9zRbi1aBXn4M6l0knBqdw4kZK3KELCHKRQwQe0npFL1iN2qawg/ wbx4cVzYp1lKBY1QtnZSL9dT5FYUf91XVuXLuYuoHgiWt79VCS/TRBCn/9j3YBpRdCb6JbcwBLV PTIVlXvcXvISp0auOtU4TOkaf1D8QrOrQbgm5zzcGB8wo/gTCjTKZ9UMfO2Y1hZweoLXwHEaAIb A6ITPMuLpV1bVi2WMyFF6ZnXupVO07Ao7b9A0MInB8ZHyHSBjZF4nTeXRzMAsq0EOuvjA0WJ1Uw WX787DymDeFySwwDd2xLfpPL1oGYezVllNB7q0rwCbASQBpJhFaI2H0sbvdRxLTbpaYjJvPFIiw i3klGA8MUf2oD5sRJfMLoWzIWR+t4jcejJJEQ2K2DQznm2pcZLmf4uYGHWzq3IfgNXnYRWV+8Nr 3f+4h1wnfrh7AMPMJZw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-12_03,2026-01-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 bulkscore=0 spamscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601120091 On 1/9/26 4:53 PM, Bjorn Helgaas wrote: > On Fri, Jan 09, 2026 at 12:51:07PM +0530, Krishna Chaitanya Chundru wrote: >> Some platforms keep the PCIe link up across bootloader and kernel >> handoff. In such cases, reinitializing the root complex is unnecessary >> if the DWC glue drivers wants to retain the PCIe link. >> >> Introduce a link_retain flag in struct dw_pcie_rp to indicate that >> the link should be preserved. When this flag is set by DWC glue drivers, >> skip dw_pcie_setup_rc() and only initialize MSI, avoiding redundant >> configuration steps. > > It sounds like this adds an assumption that the bootloader > initialization is the same as what dw_pcie_setup_rc() would do. This > assumption also applies to future changes in dw_pcie_setup_rc(). > > It looks like you mention an issue like this in [PATCH 4/5]; DBI & ATU > base being different than "HLOS" (whatever that is). This sounds like FYI, "HLOS" is a Qualcomm term for "High-Level OS".. which is a very pedantic way to say "OS" Konrad