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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab675e64dc9sm552735366b.45.2025.01.27.02.54.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 27 Jan 2025 02:54:17 -0800 (PST) Message-ID: <817ae72c-babc-4d87-b935-010b1651d301@oss.qualcomm.com> Date: Mon, 27 Jan 2025 11:54:15 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] arm64: dts: qcom: Add cpu scaling clock node To: Taniya Das , Dmitry Baryshkov Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, quic_manafm@quicinc.com References: <20241108-qcs615-mm-dt-nodes-v1-0-b2669cac0624@quicinc.com> <20241108-qcs615-mm-dt-nodes-v1-2-b2669cac0624@quicinc.com> <71635b71-71e4-4c17-add1-bf41ce770632@quicinc.com> <97f5f5b1-b4f9-4d0d-88fb-4c7a0f1c26ac@quicinc.com> <608afa23-ca4e-48dd-b929-4466560a7e61@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <608afa23-ca4e-48dd-b929-4466560a7e61@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: 6BDT-teABgGIHNXJK2xt60MCFhznHnU8 X-Proofpoint-GUID: 6BDT-teABgGIHNXJK2xt60MCFhznHnU8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-27_04,2025-01-27_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 suspectscore=0 mlxlogscore=999 clxscore=1015 spamscore=0 mlxscore=0 priorityscore=1501 adultscore=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501270087 On 20.01.2025 11:57 AM, Taniya Das wrote: > > > On 1/20/2025 4:06 PM, Dmitry Baryshkov wrote: >> On Mon, 20 Jan 2025 at 12:34, Taniya Das wrote: >>> >>> >>> >>> On 1/20/2025 2:16 PM, Dmitry Baryshkov wrote: >>>>>> This doesn't follow the bindings, does it? >>>>> I will add and re-use the closest target compatible. >>>>> >>>>>>> +          reg = <0 0x18323000 0 0x1400>, >>>>>>> +                <0 0x18325800 0 0x1400>; >>>>>>> +          reg-names = "freq-domain0", "freq-domain1"; >>>>>>> + >>>>>>> +          clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; >>>>>>> +          clock-names = "xo", "alternate"; >>>>>> Are the DCVSH interrupts? >>>>>> >>>>> This target does not have DCVSH interrupts directly connected to the >>>>> CPUFREQ-HW. >>>> So, does it require a separate LMH driver, like the one used for sdm845? >>> >>> I will check how it is handled on QCS615 as it is closer to SC7180 and I >>> didn't see any LMH handling there as well. >> >> At least sm6150-thermal.dtsi declares two LMH blocks. > > QCS615 also has 2 LMH blocks, but the handling of interrupts will be done from the LMH driver, integration with CPUFREQ-HW driver is still under evaluation. Currently platforms from the 8150 era, using drivers/thermal/qcom/lmh.c expose the LMH device as an irqchip and pass the per-instance IRQ it provides to cpufreq, instead of the latter directly consuming a GIC irq Konrad