From mboxrd@z Thu Jan 1 00:00:00 1970 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751930AbeAPLYH (ORCPT + 1 other); Tue, 16 Jan 2018 06:24:07 -0500 Received: from fllnx209.ext.ti.com ([198.47.19.16]:60709 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751898AbeAPLYD (ORCPT ); Tue, 16 Jan 2018 06:24:03 -0500 Subject: Re: [PATCH v5 01/44] dt-bindings: clock: Add new bindings for TI Davinci PLL clocks To: Adam Ford , David Lechner CC: , , , Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Kevin Hilman , References: <1515377863-20358-1-git-send-email-david@lechnology.com> <22409e49-5c14-4068-b137-7535afaf90d7@lechnology.com> <0f90b5f7-f21e-5f81-1154-9a815bbb786d@ti.com> <5aacc350-6236-2e4f-35bb-a681fc9d47e7@ti.com> <40501635-6f5b-20c9-f8bc-d17e26b58426@lechnology.com> <5832fd62-16aa-e167-7e52-2ce493e33cdc@lechnology.com> From: Sekhar Nori Message-ID: <8184c7b5-5f82-5590-9caf-fd038e1d07ac@ti.com> Date: Tue, 16 Jan 2018 16:52:53 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: Hi Adam, David, On Friday 12 January 2018 03:04 AM, Adam Ford wrote: > Thanks for clarifying. I was able to make it work with the following patch: > > diff --git a/drivers/clk/davinci/psc-da850.c b/drivers/clk/davinci/psc-da850.c > index 3b4583d..a76b8682 100644 > --- a/drivers/clk/davinci/psc-da850.c > +++ b/drivers/clk/davinci/psc-da850.c > @@ -25,7 +25,7 @@ static const struct davinci_psc_clk_info > da850_psc0_info[] __initconst = { > LPSC(9, 0, uart0, pll0_sysclk2, 0), > LPSC(13, 0, pruss, pll0_sysclk2, 0), > LPSC(14, 0, arm, pll0_sysclk6, LPSC_ALWAYS_ENABLED), > - LPSC(15, 1, dsp, pll0_sysclk1, LPSC_FORCE | LPSC_LOCAL_RESET), > + LPSC(15, 1, dsp, pll0_sysclk1, LPSC_FORCE | LPSC_LOCAL_RESET | > LPSC_ALWAYS_ENABLED), Keeping the DSP clock always enabled was not needed earlier AFAICS, so this needs to be investigated. Thanks, Sekhar