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Peter Anvin" To: Andrew Cooper , "Xin Li (Intel)" , linux-kernel@vger.kernel.org CC: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, peterz@infradead.org, seanjc@google.com Subject: =?US-ASCII?Q?Re=3A_=5BPATCH_v1_2/3=5D_x86/msr=3A_Switch_between_WRM?= =?US-ASCII?Q?SRNS_and_WRMSR_with_the_alternatives_mechanism?= User-Agent: K-9 Mail for Android In-Reply-To: References: <20240807054722.682375-1-xin@zytor.com> <20240807054722.682375-3-xin@zytor.com> Message-ID: <81CE6282-4791-42AB-9A51-4535E094D67C@zytor.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On August 9, 2024 4:07:35 PM PDT, Andrew Cooper wrote: >On 07/08/2024 6:47 am, Xin Li (Intel) wrote: >> From: Andrew Cooper >> >> Per the discussion about FRED MSR writes with WRMSRNS instruction [1], >> use the alternatives mechanism to choose WRMSRNS when it's available, >> otherwise fallback to WRMSR=2E >> >> [1] https://lore=2Ekernel=2Eorg/lkml/15f56e6a-6edd-43d0-8e83-bb64300965= 14@citrix=2Ecom/ >> >> Signed-off-by: Andrew Cooper >> Signed-off-by: Xin Li (Intel) >> --- >> arch/x86/include/asm/msr=2Eh | 28 ++++++++++++++-------------- >> 1 file changed, 14 insertions(+), 14 deletions(-) >> >> diff --git a/arch/x86/include/asm/msr=2Eh b/arch/x86/include/asm/msr=2E= h >> index d642037f9ed5=2E=2E3e402d717815 100644 >> --- a/arch/x86/include/asm/msr=2Eh >> +++ b/arch/x86/include/asm/msr=2Eh >> @@ -99,19 +99,6 @@ static __always_inline void __wrmsr(unsigned int msr= , u32 low, u32 high) >> : : "c" (msr), "a"(low), "d" (high) : "memory"); >> } >> =20 >> -/* >> - * WRMSRNS behaves exactly like WRMSR with the only difference being >> - * that it is not a serializing instruction by default=2E >> - */ >> -static __always_inline void __wrmsrns(u32 msr, u32 low, u32 high) >> -{ >> - /* Instruction opcode for WRMSRNS; supported in binutils >=3D 2=2E40= =2E */ >> - asm volatile("1: =2Ebyte 0x0f,0x01,0xc6\n" >> - "2:\n" >> - _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_WRMSR) >> - : : "c" (msr), "a"(low), "d" (high)); >> -} >> - >> #define native_rdmsr(msr, val1, val2) \ >> do { \ >> u64 __val =3D __rdmsr((msr)); \ >> @@ -312,9 +299,22 @@ do { \ >> =20 >> #endif /* !CONFIG_PARAVIRT_XXL */ >> =20 >> +/* Instruction opcode for WRMSRNS supported in binutils >=3D 2=2E40 */ >> +#define WRMSRNS _ASM_BYTES(0x0f,0x01,0xc6) >> + >> +/* Non-serializing WRMSR, when available=2E Falls back to a serializi= ng WRMSR=2E */ >> static __always_inline void wrmsrns(u32 msr, u64 val) >> { >> - __wrmsrns(msr, val, val >> 32); >> + /* >> + * WRMSR is 2 bytes=2E WRMSRNS is 3 bytes=2E Pad WRMSR with a redun= dant >> + * DS prefix to avoid a trailing NOP=2E >> + */ >> + asm volatile("1: " >> + ALTERNATIVE("ds wrmsr", > >This isn't the version I presented, and there's no discussion of the >alteration=2E > >The choice of CS over DS was deliberate, and came from Intel: > >https://www=2Eintel=2Ecom/content/dam/support/us/en/documents/processors/= mitigations-jump-conditional-code-erratum=2Epdf > >So unless Intel want to retract that whitepaper, and all the binutils >work with it, I'd suggest keeping it as CS like we use elsewhere, and as >explicitly instructed by Intel=2E > >~Andrew I looked around the kernel, and I believe we are inconsistent=2E I see bot= h 0x2e (CS) and 0x3e (DS) prefixes used for padding where open-coded=2E We can't use cs in all cases, since you can't do a store to the code segme= nt (always readonly) so we use 0x3e (DS) to patch out LOCK=2E In the paper you describe, it only mentions 0x2e as a "benign prefix" in a= specific example, not as any kind of specific recommendation=2E It is part= icularly irrelevant when it comes to padding a two instructions to the same= length as the paper deals with assignment=2E=20 If you want, I'm perfectly happy to go and ask if there is any general rec= ommendation (except for direct conditional branch hints, of course=2E)